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1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
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2023.04.03 | 23.1 | 19.1.0 |
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2021.07.23 | 21.1 | 19.1.0 | Corrected the note in Simulating PFL Design to clarify that you can perform PFL simulation using gate-level simulation, which is based on functional netlist. |
2021.06.04 | 21.1 | 19.1.0 | Corrected the constraint type for flash_data in Table: PFL Timing Constraints. |
2021.03.29 | 21.1 | 19.1.0 |
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2021.01.19 | 18.1 | 18.0 |
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Document Version | Intel® Quartus® Prime Version | Changes |
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2020.03.31 | 18.1 |
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2019.02.19 | 18.1 |
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2018.08.06 | 17.1 | Updated the calculation for the Total Clock Cycles and Total Configuration Time at 100 MHz in the Example 3. Page Mode of the Configuration Time Calculation Examples section. |
2018.07.10 | 17.1 | Updated the density for the Micron (MT29) device in the NAND Flash Memory Device Supported by PFL IP Core table. |
Date | Version | Changes |
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November 2017 | 2017.11.06 |
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October 2016 | 2016.10.31 |
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June 2016 | 2016.06.01 |
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May 2016 | 2016.05.02 |
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June 2015 | 2015.06.15 | Added support for Spansion S25FS256S and S25FS512S. |
January 2015 | 2015.01.23 |
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June 2014 | 2014.06.30 | Replaced MegaWizard Plug-In Manager information with IP Catalog. |
May 2014 | 3.2 | Updated Table 16 on page 41 to remove Stratix V limitation for the Enhanced bitstream decompression IP core option. |
May 2013 | 3.1 | Updated Table 2 on page 5 to add 28F00BP30 and 28F00BP33. |
September 2012 | 3.0 |
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August 2012 | 2.1 | Updated Table 1. |
December 2011 | 2.0 |
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February 2011 | 1.1 |
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July 2010 | 1.0 | Converted from AN386: Using the Parallel Flash Loader With the Quartus II Software. |