Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide
1.1. Avalon®-MM in Remote Update Intel® FPGA IP Core 1.2. Intel Arria 10 and Intel Cyclone® 10 GX Devices 1.3. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.4. Cyclone IV and Intel Cyclone 10 LP Devices 1.5. Flash Memory Programming Files 1.6. Design Examples 1.7. Remote Update Intel® FPGA IP User Guide Archives 1.8. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.2. Intel Arria 10 and Intel Cyclone® 10 GX Devices
1.2.1. Remote System Configuration Mode 1.2.2. Remote System Configuration Components 1.2.3. Parameter Settings 1.2.4. Ports 1.2.5. Parameters 1.2.6. Avalon-MM Interface 1.2.7. Enabling Remote System Upgrade Circuitry 1.2.8. Generating Initial RSU Image
1.2.1. Remote System Configuration Mode
1.2.1.1. Remote System Upgrade State Machine
1.2.1.1. Remote System Upgrade State Machine
1.2.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.2.6. Avalon-MM Interface
1.2.6.1. Control Status Register Signals 1.2.6.2. Register Map
1.2.6.1. Control Status Register Signals
1.2.6.1.1. Control Status Register Write Operation 1.2.6.1.2. Control Status Register Read Operation 1.2.6.1.3. Operations Example Waveforms
1.3. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon-MM Interface 1.3.7. Enabling Remote System Upgrade Circuitry
1.3.6. Avalon-MM Interface
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation
1.4. Cyclone IV and Intel Cyclone 10 LP Devices
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Remote Update Operation 1.4.7. Avalon-MM Interface 1.4.8. Enabling Remote System Upgrade Circuitry
1.4.7. Avalon-MM Interface
1.4.7.1. Control Status Register Signals 1.4.7.2. Register Map 1.4.7.3. Read Source Mapping
1.4.7.1. Control Status Register Signals
1.4.7.1.1. Control Status Register Write Operation 1.4.7.1.2. Control Status Register Read Operation
1.6. Design Examples
1.6.1. Intel Arria 10 Remote Update Design Example 1.6.2. Cyclone V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1. Remote Update Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 18.0

The Remote Update Intel® FPGA IP core implements a device reconfiguration using dedicated remote system upgrade circuitry available in supported devices. Remote system upgrade helps you deliver feature enhancements and bug fixes without recalling your product, reduces time-to-market, and extends product life. The Remote Update Intel® FPGA IP core commands the configuration circuitry to start a reconfiguration cycle.

The dedicated circuitry performs error detection during and after the configuration process. When the dedicated circuitry detects errors, the circuitry facilitates system recovery by reverting back to a safe, default factory configuration image and then provides error status information.

The following figures shows a functional diagram for a typical remote system upgrade process.

Figure 1. Typical Remote System Upgrade Process
Note: Intel® recommends that you use the following Remote Update Intel® FPGA IP core input clock (fMAX) values:
  • 10 MHz—for Arria® II and Stratix® IV devices
  • 20 MHz—for other supported devices
Figure 2. High-Level Block Diagram of Remote System Upgrade
Note: The remote system upgrade feature support for each configuration scheme varies between device family. For more information about the configuration scheme and the remote system upgrade feature, please refer to the configuration chapter of the respective device family handbook.
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