Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 8/16/2022
Public
Document Table of Contents

1.3.6.1. Control Status Register Signals

Table 11.  Remote Update Intel® FPGA IP Core Avalon® -MM Control Status Register Signals for Arria® II, Arria® V, Cyclone® V, Stratix® IV, and Stratix® V Devices
Name Width Direction Description
clk 1 Input Clock input.
reset 1 Input Reset input.
avl_csr_address 3 Input Address bus.
avl_csr_read 1 Input Perform a read transaction.
avl_csr_write 1 Input Perform a write transaction.
avl_csr_readdata 32 Output Read data from IP.
avl_csr_readdata_valid 1 Output Indicate when read data is valid.
avl_csr_writedata 32 Input Write data to IP.
avl_csr_waitrequest 1 Output Waitrequest signal high indicates the core is busy.

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