Remote Update Intel® FPGA IP User Guide

ID 683695
Date 8/16/2022

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Document Table of Contents Register Map

Table 6.  Remote Update Intel® FPGA IP Core Avalon® -MM Register Map for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
  • The IP core can read or write each field separately as each command has different parameter value.
  • The default value for the registers is 0.
Register Name Address Offset Width R/W Description
RU_RECONFIG_TRIGGER_CONDITIONS 0x0 5 Read Read configuration trigger conditions.
  • Bit 4—wdtimer_source: User watchdog timer timeout
  • Bit 3—nconfig_source: External configuration reset (nCONFIG) assertion.
  • Bit 2—runconfig_source: Configuration reset triggered from logic array
  • Bit 1—nstatus_source: nSTATUS asserted by an external device as the result of an error
  • Bit 0—crcerror_source: CRC error during application configuration.
RU_WATCHDOG_TIMEOUT 0x1 12 Read/Write Read or write watchdog timeout value.
RU_WATCHDOG_ENABLE 0x2 1 Read/Write Enable or disable watchdog timeout.
  • 0: Disable
  • 1: Enable
RU_PAGE_SELECT 0x3 24 or 32 Read/Write Read or write start address of the configuration image.
RU_CONFIGURATION_MODE 0x4 1 Read/Write Write configuration mode set to 1 in application page and 0 in factory page.
RU_RESET_TIMER 0x5 1 Write

Write a value of 1 to this register to trigger reset timer of the remote update. The IP will automatically trigger a reset pulse to the reset timer pin of the remote update.

RU_RECONFIG 0x6 1 Write

Write a value of 1 to this register to trigger reconfiguration from a new image. The IP will set 1 to the reconfig pin of the remote update and hold this value until the process done.

RU_CTL_NUPDT 0x7 1 Write Allow capturing of data from either Control/Update register by controlling ctl_nupdt.
  • 0: Capture value from Update Register
  • 1: Capture data from Control Register