Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 7/13/2021
Public
Document Table of Contents

1.2.1.1. Remote System Upgrade State Machine

After power-up and exit POR, the remote system upgrade registers are reset to 0 and the factory or application configuration image is loaded based on the start address stored at 0x00 to 0x1F in the configuration device or QSPI flash. The Remote Update Intel® FPGA IP core enables you to perform the following remote update functions once the factory or an application image is loaded successfully:

  • Switch from factory image to application image
  • In DTA mode, switch from initial application image to others application image

The configuration mode (AnF) bit is by default set to 0 in the DTA mode, the AnF bit cannot be used to indicate the type (such as factory or application image) of image loaded into the FPGA. In the DTA mode, the watchdog timer is disabled by default. You cannot enable the watchdog timer in the initial or first application image loaded upon powering up the device. You can enable the watchdog timer feature when you perform remote update from the initial application image to other application image.

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