Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 7/13/2021
Public
Document Table of Contents

1.4.7.2. Register Map

Table 20.  Remote Update Intel® FPGA IP Core Avalon® -MM Register Map for Cyclone® IV and Intel® Cyclone® 10 LP Devices
  • The last two bits of an address represents the read_source signals.
  • You have to write the correct address offset to carry read_source value as shown in the Read Source Mapping table.
  • The IP core combines the address bus of control status register interface to the read_source parameter.
  • The default value for the registers is 0.
  • The address offsets are in word.
Register Name Address Offset Width R/W Description
RU_MASTER_SM_CURRENT_STATE_MODE 0x0 2 Read

Read current state of the state machine

00: Factory mode

01: Application mode

11: Application mode with the master state machine user watchdog timer enabled.

RU_FORCE_EARLY_CONF_DONE 0x4 1 Read/Write Force early CONF_DONE
RU_WATCHDOG_TIMEOUT 0x8 29 or 12 Read/Write Read or write watchdog timeout value.
  • 12 bit wide when writing
  • 29 bit wide when reading
RU_WATCHDOG_ENABLE 0xC 1 Read/Write Enable or disable watchdog timeout.
  • 0: Disable
  • 1: Enable
RU_BOOT_ADDRESS
0x10 24, 29 or 32 Read/Write
  • 29 or 32 bit wide (EPCQ 32 bit addressing) when reading boot address.
  • 24 or 32 bit wide when writing the boot address.
RU_FORCE_INTERNAL_OSC 0x14 1 Read/Write Force the internal oscillator as startup state machine clock (osc_int) option bit
RU_RECONFIG_TRIGGER_CONDITIONS 0x18 5 Read Read configuration trigger conditions.
  • Bit 4—nconfig_source: External configuration reset (nCONFIG) assertion.
  • Bit 3—crcerror_source: CRC error during application configuration.
  • Bit 2—nstatus_source: nSTATUS asserted by an external device as the result of an error
  • Bit 1—wdtimer_source: Users watchdog timer timeout
  • Bit 0—runconfig_source: Configuration reset triggered from logic array
RU_RESET_TIMER 0x1C 1 Write

Write a value of 1 to this register to trigger reset timer of the remote update. The IP core will automatically trigger a reset pulse to reset timer pin of the remote update.

RU_RECONFIG 0x1D 1 Write

Write to this address with value of 1 to trigger reconfiguration from a new image. The IP core will set 1 to reconfig pin of the remote update and hold this value until the process done.

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