Remote Update Intel® FPGA IP User Guide

ID 683695
Date 7/13/2021
Document Table of Contents

1.2.5. Parameters

Table 4.  Parameter Type and Corresponding Parameter Bit Width Mapping for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Bit Parameter Width Comments
000 Reconfiguration trigger conditions (Read Only) 5
  • Bit 4—wdtimer_source: User watchdog timer timeout.
  • Bit 3—nconfig_source: External configuration reset (nCONFIG) assertion.
  • Bit 2—runconfig_source: Configuration reset triggered from logic array.
  • Bit 1—nstatus_source: nSTATUS asserted by an external device as the result of an error.
  • Bit 0—crcerror_source: CRC error during application configuration.
The POR value for all bits are 0.
001 Illegal Value
010 Watchdog Timeout Value 12 Width of 12 when writing.

The 12 bits for writing are the upper 12 bits (left-most or most-significant bits) of the 29-bit Watchdog Timeout Value.

When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001.

29 Width of 29 when reading.
011 Watchdog Enable 1
100 Page Select 32

For the Intel® Quartus® Prime software version 14.0 and later:

  • Width of 32 when reading and writing the start address.
  • For active serial devices using 32-bit addressing, such as EPCQL-256, PGM[31..2] corresponds to the upper 30 bits of the 32-bits start address. PGM[1..0] is read as 2'b0.
101 Configuration Mode (AnF) 1

This parameter is set to 1 in application page and is set to 0 in factory page. In remote update mode, this parameter can be read and written.

Before loading the application page in remote update mode, Intel® recommends that you set this parameter to 1. The content of the control register cannot be read properly if you fail to do so.

110 Illegal Value
111 Illegal Value

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