AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

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ID 683662
Date 10/08/2018
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Document Table of Contents
Document Table of Contents x
Tutorial Overview Tutorial Walkthrough Tutorial Results Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design
Tutorial Overview x
PR Debug Considerations Tutorial Software and Hardware Requirements Tutorial Design Description Downloading the Tutorial Design
Downloading the Tutorial Design x
Tutorial Design Files
Tutorial Walkthrough x
Step 1: Getting Started Step 2: Preparing the Base Revision Step 3: Preparing the Implementation Revisions for Debug Step 4: Tapping Signals in the Implementation Persona Step 5: Configuring Data Acquisition Step 6: Setting Trigger Conditions Step 7: Generating Programming Files Step 8: Programming the Board Step 9: Performing Data Acquisition
Step 2: Preparing the Base Revision x
Preparing the Static Region Preparing the Default PR Persona
Step 5: Configuring Data Acquisition x
Add Acquisition Clock Add Storage Parameters
Tutorial Results x
Waveforms for Slow Implementation Waveforms for Default Implementation Waveforms for Empty Implementation
Tutorial Overview
Tutorial Walkthrough
Tutorial Results
Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

Tutorial Overview

Updated for:
Intel® Quartus® Prime Design Suite 18.1
This document demonstrates how to debug an Intel® Arria® 10 Partial Reconfiguration design with the Signal Tap Logic Analyzer. This application note extends the Partial Reconfiguration (PR) work presented on AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board to a verification environment.

The Signal Tap Logic Analyzer captures and displays real-time signal behavior in an FPGA design, allowing to examine the behavior of internal signals during normal device operation without the need for extra I/O pins or external lab equipment.

Partial Reconfiguration is an advanced design flow that allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can define multiple personas to occupy the same design region, without impacting operation in other regions.

The PR support in the Signal Tap Logic Analyzer includes data acquisition in static and PR regions. Moreover, you can debug multiple personas present in a PR region and multiple PR regions.

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