AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

ID 683662
Date 10/08/2018

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Tutorial Overview

Updated for:
Intel® Quartus® Prime Design Suite 18.1
This document demonstrates how to debug an Intel® Arria® 10 Partial Reconfiguration design with the Signal Tap Logic Analyzer. This application note extends the Partial Reconfiguration (PR) work presented on AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board to a verification environment.

The Signal Tap Logic Analyzer captures and displays real-time signal behavior in an FPGA design, allowing to examine the behavior of internal signals during normal device operation without the need for extra I/O pins or external lab equipment.

Partial Reconfiguration is an advanced design flow that allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can define multiple personas to occupy the same design region, without impacting operation in other regions.

The PR support in the Signal Tap Logic Analyzer includes data acquisition in static and PR regions. Moreover, you can debug multiple personas present in a PR region and multiple PR regions.