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Ixiasoft
Step 1: Getting Started
Step 2: Preparing the Base Revision
Step 3: Preparing the Implementation Revisions for Debug
Step 4: Tapping Signals in the Implementation Persona
Step 5: Configuring Data Acquisition
Step 6: Setting Trigger Conditions
Step 7: Generating Programming Files
Step 8: Programming the Board
Step 9: Performing Data Acquisition
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Ixiasoft
Step 7: Generating Programming Files
The design is now ready for compilation. The Intel® Quartus® Prime Compiler generates files that you then program into the FPGA. This Partial Reconfiguration design requires generating .sof and .rbf files.
- Ensure the blinking_led.qsf contains the following assignments:
These assignments allow the assembler to automatically generate the required PR bitstreams.set_global_assignment -name GENERATE_PR_RBF_FILE ON set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
- In the Intel® Quartus® Prime GUI, click Processing > Start Compilation to compile the base revision.
Alternatively, type the following command:
quartus_sh --flow compile blinking_led -c blinking_led
- Compile the implementation revision:
quartus_sh --flow compile blinking_led –c blinking_led_slow quartus_sh --flow compile blinking_led –c blinking_led_default quartus_sh --flow compile blinking_led –c blinking_led_empty
If the compilation succeeds, the output files are now in the output_files directory.