AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

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ID 683662
Date 10/08/2018
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Document Table of Contents
Document Table of Contents x
Tutorial Overview Tutorial Walkthrough Tutorial Results Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design
Tutorial Overview x
PR Debug Considerations Tutorial Software and Hardware Requirements Tutorial Design Description Downloading the Tutorial Design
Downloading the Tutorial Design x
Tutorial Design Files
Tutorial Walkthrough x
Step 1: Getting Started Step 2: Preparing the Base Revision Step 3: Preparing the Implementation Revisions for Debug Step 4: Tapping Signals in the Implementation Persona Step 5: Configuring Data Acquisition Step 6: Setting Trigger Conditions Step 7: Generating Programming Files Step 8: Programming the Board Step 9: Performing Data Acquisition
Step 2: Preparing the Base Revision x
Preparing the Static Region Preparing the Default PR Persona
Step 5: Configuring Data Acquisition x
Add Acquisition Clock Add Storage Parameters
Tutorial Results x
Waveforms for Slow Implementation Waveforms for Default Implementation Waveforms for Empty Implementation
Tutorial Overview
Tutorial Walkthrough
Tutorial Results
Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

Step 9: Performing Data Acquisition

After loading the appropriate .rbf onto the board, you can start data acquisition on the Signal Tap logic analyzer.

To perform data acquisition:

  1. Make sure that the Signal Tap Logic Analyzer loads the .stp file in the current active revision.
  2. In the top right corner of the Signal Tap window, set up the JTAG connection to the board with the following options:
    Option Description
    Hardware USB-BlasterII
    Device 10AT115S
    Bridge Index 0
    Figure 20. JTAG Configuration
  3. On the Signal Tap toolbar, click Run Analysis .
    The analysis may take a few minutes.
    When the analysis finishes, the Signal Tap Logic Analyzer loads the waveforms to the window.
The following section displays the resultant waveforms for all PR configurations.
Level Two Title