AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

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ID 683662
Date 10/08/2018
Public

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Document Table of Contents
Document Table of Contents x
Tutorial Overview Tutorial Walkthrough Tutorial Results Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design
Tutorial Overview x
PR Debug Considerations Tutorial Software and Hardware Requirements Tutorial Design Description Downloading the Tutorial Design
Downloading the Tutorial Design x
Tutorial Design Files
Tutorial Walkthrough x
Step 1: Getting Started Step 2: Preparing the Base Revision Step 3: Preparing the Implementation Revisions for Debug Step 4: Tapping Signals in the Implementation Persona Step 5: Configuring Data Acquisition Step 6: Setting Trigger Conditions Step 7: Generating Programming Files Step 8: Programming the Board Step 9: Performing Data Acquisition
Step 2: Preparing the Base Revision x
Preparing the Static Region Preparing the Default PR Persona
Step 5: Configuring Data Acquisition x
Add Acquisition Clock Add Storage Parameters
Tutorial Results x
Waveforms for Slow Implementation Waveforms for Default Implementation Waveforms for Empty Implementation
Tutorial Overview
Tutorial Walkthrough
Tutorial Results
Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

Tutorial Software and Hardware Requirements

To perform this tutorial, you need the following software and hardware:
  • The Intel® Quartus® Prime Pro Edition software version 18.1 or later. The software includes the Signal Tap Logic Analyzer and the Programmer.
  • Intel® Arria® 10 GX FPGA development kit, or a design board with JTAG connection to the device under test.
  • Intel® FPGA Download Cable, for communication between the device and the Intel® Quartus® Prime software.
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