AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

ID 683662
Date 10/08/2018

A newer version of this document is available. Customers should click here to go to the newest version.

Preparing the Static Region

  1. In the IP Catalog (Tools > IP Catalog), type SLD JTAG Bridge Agent, and double-click the SLD JTAG Bridge Agent Intel® FPGA IP .
  2. In the Create IP Variant dialog box, type sld_agent as the file name, and then click Create.
    Figure 5. Create IP Variant Dialog Box
  3. In the parameter editor, use the default parameterization for sld_agent. Click Generate HDL..., and then click Generate.
    Figure 6. SLD JTAG Bridge Agent Intel® FPGA IP Parameters
    The parameter editor generates the sld_agent.ip IP variation file and adds the file to the blinking_led project.
  4. Close the parameter editor.
  5. Verify whether the sld_agent IP variant appears in the IP Components tab of the Project Navigator.
    Figure 7. sld_agent IP Variant in Project Navigator
    If the IP variant does not appear in the Project Navigator, click Project > Add/Remove Files in Project, find the sld_agent.ip file, and add to the project.
  6. In the file, instantiate the sld_agent IP in the base revision by uncommenting the following lines:
    //Enable Signal Tap
    wire tck;
    wire tms;
    wire tdi;
    wire vir_tdi;
    wire ena;
    wire tdo;
    sld_agent u_sld_agent (
        .tck	(tck),	//  output,  width = 1, connect_to_bridge_host.tck
        .tms	(tms),	//  output,  width = 1,                       .tms
        .tdi	(tdi),	//  output,  width = 1,                       .tdi
        .vir_tdi(vir_tdi),	//output,  width = 1,                 .vir_tdi
        .ena	(ena),	//  output,  width = 1,                       .ena
        .tdo	(tdo)	 //   input,  width = 1,                       .tdo