AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

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ID 683662
Date 10/08/2018
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Document Table of Contents
Document Table of Contents x
Tutorial Overview Tutorial Walkthrough Tutorial Results Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design
Tutorial Overview x
PR Debug Considerations Tutorial Software and Hardware Requirements Tutorial Design Description Downloading the Tutorial Design
Downloading the Tutorial Design x
Tutorial Design Files
Tutorial Walkthrough x
Step 1: Getting Started Step 2: Preparing the Base Revision Step 3: Preparing the Implementation Revisions for Debug Step 4: Tapping Signals in the Implementation Persona Step 5: Configuring Data Acquisition Step 6: Setting Trigger Conditions Step 7: Generating Programming Files Step 8: Programming the Board Step 9: Performing Data Acquisition
Step 2: Preparing the Base Revision x
Preparing the Static Region Preparing the Default PR Persona
Step 5: Configuring Data Acquisition x
Add Acquisition Clock Add Storage Parameters
Tutorial Results x
Waveforms for Slow Implementation Waveforms for Default Implementation Waveforms for Empty Implementation
Tutorial Overview
Tutorial Walkthrough
Tutorial Results
Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

Step 6: Setting Trigger Conditions

These steps direct the Signal Tap Logic Analyzer to record data only after u_blinking_led|led_three_on or u_blinking_led|led_two_on does a rising edge transition.

  1. In the Setup tab of the Signal Tap Logic Analyzer window, turn on the box under the Trigger Condition column
  2. Open the drop-down menu and select Basic OR.
  3. For u_blinking_led|led_three_on and u_blinking_led|led_two_on, turn on Trigger Enable and select Rising Edge as the trigger type.
  4. For all the other signals, turn off Trigger Enable.
Figure 19. Trigger Conditions

Defining trigger conditions completes the Signal Tap instance configuration. Now you can compile the design.

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