AN 797: Partially Reconfiguring a Design: on Intel® Arria® 10 GX FPGA Development Board

ID 683497
Date 12/11/2020
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Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board

Updated for:
Intel® Quartus® Prime Design Suite 20.3
This application note demonstrates transforming a simple design into a partially reconfigurable design and implementing the design on the Intel® Arria® 10 GX FPGA development board.

The partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can create multiple personas for a particular region in your design, without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. The current version of the software introduces a new and simplified compilation flow for partial reconfiguration.

Partial reconfiguration has the following advantages over a flat design:
  • Allows run-time design reconfiguration
  • Increases scalability of the design
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption through efficient use of board space

Implementation of this reference design requires basic familiarity with the Intel® Quartus® Prime FPGA implementation flow and knowledge of the primary Intel® Quartus® Prime project files. This tutorial uses the Intel® Arria® 10 GX FPGA development board on the bench, outside of the PCIe* slot in your workstation.