AN 797: Partially Reconfiguring a Design: on Intel® Arria® 10 GX FPGA Development Board

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ID 683497
Date 12/11/2020
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration Controller IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 9: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board

Setting the Base Revision Type

  1. Click Project > Revisions.
  2. Ensure that the blinking_led revision is set as the current revision.
  3. To set the revision type for blinking_led, double-click the Revision Type cell, select Partial Reconfiguration - Base, and click OK.
  4. Verify that the blinking_led.qsf now contains the following assignment: 
    ##blinking_led.qsf
set_global_assignment -name REVISION_TYPE PR_BASE
Level Two Title