AN 797: Partially Reconfiguring a Design: on Intel® Arria® 10 GX FPGA Development Board
ID
683497
Date
12/11/2020
Public
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration Controller IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Reference Design Files
The partial reconfiguration tutorial is available in the following location:
https://github.com/intel/fpga-partial-reconfig
To download the tutorial:
- Click Clone or download.
- Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
- Navigate to the tutorials/a10_pcie_devkit_blinking_led sub-folder to access the reference design.
The flat folder consists of the following files:
File Name | Description |
---|---|
top.sv | Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module. |
top_counter.sv | Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module. |
blinking_led.sdc | Defines the timing constraints for the project. |
blinking_led.sv | This module acts as the PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3]. |
blinking_led.qpf | Intel® Quartus® Prime project file containing the list of all the revisions in the project. |
blinking_led.qsf | Intel® Quartus® Prime settings file containing the assignments and settings for the project. |
Note:
The pr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.
Figure 2. Reference Design Files