AN 797: Partially Reconfiguring a Design: on Intel® Arria® 10 GX FPGA Development Board

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ID 683497
Date 12/11/2020
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration Controller IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 9: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board

Step 1: Getting Started

To copy the reference design files to your working environment and compile the blinking_led flat design:
  1. Create a directory in your working environment, a10_pcie_devkit_blinking_led_pr.
  2. Copy the downloaded tutorials/a10_pcie_devkit_blinking_led/flat sub-folder to the directory, a10_pcie_devkit_blinking_led_pr.
  3. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
  4. To compile the flat design, click Processing > Start Compilation.
Level Two Title