AN 797: Partially Reconfiguring a Design: on Intel® Arria® 10 GX FPGA Development Board
ID
683497
Date
12/11/2020
Public
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration Controller IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Reference Design Overview
This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50 MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 1. Flat Reference Design without PR Partitioning