AN 797: Partially Reconfiguring a Design: on Intel® Arria® 10 GX FPGA Development Board

ID 683497
Date 12/11/2020
Public

AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board Revision History

Date Intel® Quartus® Prime Version Changes
2020.12.11 20.3
  • Corrected link in "Partially Reconfiguring a Design on Intel Arria 10 GX FPGA Development Board" topic.
  • Deleted repeated sentence in "Creating a Design Partition" topic.".
  • Added link to "Adding the Partial Reconfiguration Controller IP" topic.
  • Corrected typo in "Compiling the Base Revision" topic.
  • Added figure title to "Preparing PR Implementation Revisions." topic.
2020.12.07 20.3
  • Updated version support to 20.3.
  • Corrected IP name in "Adding the Partial Reconfiguration IP Core" topic.
  • Updated steps in "Creating Implementation Revisions" topic.
2019.09.10 19.1 Corrected typos in "Adding the Partial Reconfiguration Controller IP" topic.
2019.07.15 19.1
  • Updated version support to 19.1.
  • Updated default .qdb export location from output_files to project directory.
  • Updated for changes to Design Partition command submenu changes, including change of "periphery reuse core" to "reserved core."
  • Updated references to the name of Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
  • Updated QSF examples for latest version.
  • Updated all screenshots for latest version.
  • Removed statement about "new" simplified flow. This flow is no longer new.
  • Updated references to Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.
2018.09.24 18.1
  • Updated sections - Step 2: Creating a Design Partition, Step 7: Compiling the Base Revision and Exporting the Static Region, and Step 8: Preparing PR Implementation Revisions with the new PR flow that eliminates the need for manual export of finalized snapshot of the static region.
  • Other minor text edits and image updates.
2018.05.07 18.0
  • Compilation flow change
  • Other minor text edits

2017.11.06

17.1

  • Updated the Reference Design Requirements section with software version
  • Updated the Flat Reference Design without PR Partitioning figure with design block changes
  • Updated the Reference Design Files table with information on the Top_counter.sv module
  • Updated the Partial Reconfiguration IP Core Integration figure with design block changes
  • Updated the figures - Design Partitions Window and Logic Lock Regions Window to reflect the new GUI
  • Text edits

2017.05.08

17.0

  • Updated software version in Reference Design Requirements section
  • Added information about enable freeze interface option in Step 4: Adding the Partial Reconfiguration IP Core section
  • Added information on the importance of SDC ordering in Step 4: Adding the Partial Reconfiguration IP Core section
  • Added an overview on base, synthesis, and implementation revisions in Step 6: Creating Revisions section
  • Text edits

2016.12.21

16.1

Initial release of the document

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