Nios® V Processor Reference Manual

ID 683632
Date 6/30/2022

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Document Table of Contents

2.3. Processor Architecture

This section describes the hardware structure of the Nios® V/m processor, including a discussion on all the functional units of the processor architecture and the fundamentals of the processor hardware implementation. The Nios® V/m processor architecture describes an instruction set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions.
The Nios® V/m processor architecture defines the following functional units:
  • General Purpose Register file
  • Arithmetic Logic Unit (ALU)
  • Control and Status Registers (CSR)
  • Exception Controller
  • Interrupt Controller
  • Instruction Bus
  • Data Bus
  • RISC-V based Debug Module
Figure 2.  Nios® V/m Processor Core Block Diagram