Nios® V Processor Reference Manual

ID 683632
Date 6/30/2022

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2.3.5. Exception Controller

Nios® V/m processor architecture provides a simple exception controller to handle all exception types. Each exception, including internal hardware interrupts, causes the processor to transfer execution to an exception address. An exception handler at this address determines the cause of the exception and then executes an appropriate exception routine. You can set the exception address in the Nios® V/m Processor IP parameterization. Nios® V/m stores the address, which is writable, in Machine Trap Handler Base Address (mtvec) CSR register.

All exceptions are precise, which means that the processor completes all instructions preceding the faulting instruction and does not start the execution of instructions following the faulting instruction.

Table 6.  Exceptions
Exception Description
Instruction Address Misaligned The core pipeline logic in F-stage detects the exception. This exception is flagged if the core fetched a Program Counter that is not aligned to a 32-bit word boundary.
Instruction Access Fault Instruction read response signal detects this exception.
Illegal Instruction Instruction decoder in D-stage flags this exception if an instruction word contains encoding for an unimplemented or undefined instruction.

Control logic for CSR read/write flags this exception in E-stage if a CSR instruction accesses an unimplemented or undefined CSR.

Breakpoint Instruction decoder flags the software breakpoint exception EBREAK in the D-stage.
Load Address Misaligned The core for load/store unit in M-stage detects the misalignment. This exception is flagged if the data address is not aligned to the size of the data access.
Store Address Misaligned
Load Access Fault The core for data read/write response signal detects the exception.
Store Access Fault
Env call from M-mode Instruction decoder in D-stage detects the instruction.