Nios® V Processor Reference Manual

ID 683632
Date 6/30/2022

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Document Table of Contents Instruction Manager Port

Nios® V/m processor instruction bus is implemented as a 32-bit AMBA* 4 AXI manager port.

The instruction manager port:
  • Performs a single function: it fetches instructions to be executed by the processor.
  • Does not perform any write operations.
  • Can issue successive read requests before data return from prior requests.
  • Can prefetch sequential instructions.
  • Always retrieves 32-bit of data. Every instruction fetch returns a full instruction word, regardless of the width of the target memory. The widths of memory in the Nios® V/m processor system is not applicable to the programs. Instruction address is always aligned to a 32-bit word boundary.
Table 8.  Instruction Interface Signals
Interface Signal Role Direction
Write Address Channel awaddr Unused Output
awprot Unused Output
awsize Unused Output
awready Unused Input
Write Data Channel wvalid Unused Output
wdata Unused Output
wstrb Unused Output
wlast Unused Output
wready Unused Input
Write Response Channel bvalid Unused Input
bres Unused Input
bready Unused Output
Read Address Channel araddr Instruction Address (Program Counter) Output
arprot Unused- tied off to constant value Output
arvalid Instruction request valid Output
arsize Constant 2- 4 bytes Output
arready From subordinate/interconnect Input
Read Data Channel rdata Instruction Input
rvalid Instruction valid Input
rresp Instruction response: Non-zero value denotes instruction access fault exception. Input
rready Constant 1 Output