A newer version of this document is available. Customers should click here to go to the newest version.
2.3.7. Memory and I/O Organization
This section explains hardware implementation details of the Nios® V/m processor memory and I/O organization. The discussion covers both general concepts true for all Nios® V/m processor systems, as well as features that might varies from system to system.
Nios® V/m processor systems are configurable. As a result, the memory and I/O organization varies from system to system. A Nios® V/m processor core uses one or more of the following to provide memory and I/O access:
- Instruction manager port: An Arm* Advanced Microcontroller Bus Architecture ( AMBA* ) 4 AXI Memory-Mapped manager port that connects to instruction memory via system interconnect fabric.
- Data manager port: An AMBA* 4 AXI Memory-Mapped manager port that connects to data memory and peripherals via the system interconnect fabric.
Nios® V/m Processor Core Memory Mapped I/O Access: Both data memory and peripherals are mapped into the address space of the data manager port. Nios® V/m processor core uses little-endian byte ordering. Words and halfwords are stored in memory with the more-significant bytes at higher addresses. The Nios® V/m processor core does not specify anything about the existence of memory and peripherals. The quantity, type, and connection of memory and peripherals are system dependent.
Instruction and Data Buses
Did you find the information on this page useful?