Nios® V Processor Reference Manual

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ID 683632
Date 6/30/2022
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Document Table of Contents
Document Table of Contents x
1. About this Document 2. Nios® V/m Processor 3. Nios V Processor Reference Manual Archives 4. Document Revision History for the Nios® V Processor Reference Manual
1. About this Document x
1.1. Overview
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Control and Status Registers 2.3.5. Exception Controller 2.3.6. Interrupt Controller 2.3.7. Memory and I/O Organization 2.3.8. RISC-V based Debug Module
2.3.6. Interrupt Controller x
2.3.6.1. Timer and Software Interrupt Module
2.3.7. Memory and I/O Organization x
2.3.7.1. Instruction and Data Buses
2.3.7.1. Instruction and Data Buses x
2.3.7.1.1. Instruction Manager Port 2.3.7.1.2. Data Manager Port 2.3.7.1.3. Address Map
2.3.8. RISC-V based Debug Module x
2.3.8.1. Debug Mode 2.3.8.2. Halt from Debug Module 2.3.8.3. Debug Implementation 2.3.8.4. Abstract Commands in Debug Mode 2.3.8.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. About this Document
2. Nios® V/m Processor
3. Nios V Processor Reference Manual Archives
4. Document Revision History for the Nios® V Processor Reference Manual

2.3.7. Memory and I/O Organization

This section explains hardware implementation details of the Nios® V/m processor memory and I/O organization. The discussion covers both general concepts true for all Nios® V/m processor systems, as well as features that might varies from system to system.

Nios® V/m processor systems are configurable. As a result, the memory and I/O organization varies from system to system. A Nios® V/m processor core uses one or more of the following to provide memory and I/O access:

  • Instruction manager port: An Arm* Advanced Microcontroller Bus Architecture ( AMBA* ) 4 AXI Memory-Mapped manager port that connects to instruction memory via system interconnect fabric.
  • Data manager port: An AMBA* 4 AXI Memory-Mapped manager port that connects to data memory and peripherals via the system interconnect fabric.

Nios® V/m Processor Core Memory Mapped I/O Access: Both data memory and peripherals are mapped into the address space of the data manager port. Nios® V/m processor core uses little-endian byte ordering. Words and halfwords are stored in memory with the more-significant bytes at higher addresses. The Nios® V/m processor core does not specify anything about the existence of memory and peripherals. The quantity, type, and connection of memory and peripherals are system dependent.


Section Content
Instruction and Data Buses

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