Nios® V Processor Reference Manual

ID 683632
Date 6/30/2022

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Document Table of Contents

2.3.3. Reset and Debug Signals

Signal Name Type Description
reset Input This is a global hardware reset signal that forces the Nios® V processor core to reset immediately.
dbg_reset Output
The following are the characteristics of the reset output signal:
  • Visible when you enable the option Enable Debug.
  • Triggered by the JTAG debugger
  • Internally routed to the Nios® V processor core and timer module. This allows the JTAG debugger to reset the processor and the timer module.
  • Can be connected to the reset input signal of other components as needed.