Nios® V Processor Reference Manual

ID 683632
Date 6/30/2022

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Document Table of Contents Debug Mode

You can enter the debug mode, as specified in the RISC-V architecture specification, in two ways:

  1. Halt from Debug Module
  2. Software breakpoints

Debug Module selects Hardware Thread (Hart); which can be in one of the following four states:

  1. Non-existent: Debug Module probes a hart which does not exist.
  2. Unavailable: Reset or temporary shutdown.
  3. Running: Normal operation outside of debug.
  4. Halted: Hart is said to be halted when it is in debug mode.