Nios® V Processor Reference Manual

ID 683632
Date 6/30/2022

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Document Table of Contents Address Map

The address map for memories and peripherals in a Nios® V/m processor system is design dependent. There are four addresses that are part of the processor:
  1. Reset Address
  2. Debug Exception Address
  3. Exception Address
  4. Timer and Software Interrupt Address

You can specify the Reset Address and Debug Exception Address in Platform Designer during system configuration. You can modify the Exception Address which is stored in the mvtec register. mvtime and mtimecmp register controls the timer interrupt and the msip register bit controls the software interrupt.