Nios® V Processor Reference Manual

ID 683632
Date 6/30/2022

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Document Table of Contents Debug Implementation

Assertion of haltreq bit send an asynchronous interrupt to the core logic. Core logic completes the instruction in W-stage. By the order of priority, instruction in M-stage, E-stage, D-stage or F-stage, takes the interrupt.
  • When there is a valid instruction in M-stage, the Program Counter writes to the Debug Program Counter.
  • If the instruction in M-stage is not valid, then instruction in E-stage can be interrupted and so on and so forth.
  • When there is no valid instruction in the pipe, the Program Counter for the next instruction to be executed writes to the Debug Program Counter.
For branches, the next Program Counter depends on whether a branch was taken or not, and whether the prediction (if any) was correct.
Figure 3. Debug Module Block Diagram