Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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3.3.8.3. Name HDL Signals for Automatic Interface and Type Recognition in the Platform Designer Component Editor

If you create the component's top-level HDL file before using the Component Editor, the Component Editor recognizes the interface and signal types based on the signal names in the source HDL file. This auto-recognition feature eliminates the task of manually assigning each interface and signal type in the Component Editor.

To enable auto-recognition, you must create signal names using the following naming convention:

<interface type prefix>_<interface name>_<signal type>

Specifying an interface name with <interface name> is optional if you have only one interface of each type in the component definition. For interfaces with only one signal, such as clock and reset inputs, the <interface type prefix> is also optional.

Table 32.  Interface Type Prefixes for Automatic Signal Recognition When the Component Editor recognizes a valid prefix and signal type for a signal, it automatically assigns an interface and signal type to the signal based on the naming convention. If no interface name is specified for a signal, you can choose an interface name on the Signals & Interfaces tab in the Component Editor.
Interface Prefix Interface Type
asi

Avalon® Streaming sink (input)

aso

Avalon® Streaming source (output)

avm

Avalon® memory-mapped host

avs

Avalon® memory-mapped agent

axm AXI master
axs AXI slave
apm APB master
aps APB slave
coe Conduit
csi Clock Sink (input)
cso Clock Source (output)
inr Interrupt receiver
ins Interrupt sender
ncm

Nios® II custom instruction master

ncs

Nios® II custom instruction slave

rsi Reset sink (input)
rso Reset source (output)
tcm

Avalon® TC host

tcs

Avalon® TC agent

Refer to the Avalon® Interface Specifications or the AMBA* Protocol Specification for the signal types available for each interface type.