Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.2.1.5. Timing Adapter

The timing adapter allows you to connect component interfaces that require a different number of cycles before driving or receiving data. This adapter inserts a FIFO buffer between the source and sink to buffer data or pipeline stages to delay the back-pressure signals. You can also use the timing adapter to connect interfaces that support the ready signal, and those that do not. The timing adapter treats all signals other than the ready and valid signals as payload, and simply drives them from the source to the sink.
Table 62.  Timing Adapter Adaptations

Condition

Adaptation

The source has ready, but the sink does not.

In this case, the source can respond to backpressure, but the sink never needs to apply it. The ready input to the source interface is connected directly to logical 1.

The source does not have ready, but the sink does.

The sink may apply backpressure, but the source is unable to respond to it. There is no logic that the adapter can insert that prevents data loss when the source asserts valid but the sink is not ready. The adapter provides simulation time error messages if data is lost. The user is presented with a warning, and the connection is allowed.

The source and sink both support backpressure, but the sink’s ready latency is greater than the source's.

The source responds to ready assertion or deassertion faster than the sink requires it. The number of pipeline stages equal to the difference in ready latency are inserted in the ready path from the sink back to the source, causing the source and the sink to see the same cycles as ready cycles.

The source and sink both support backpressure, but the sink’s ready latency is less than the source's.

The source cannot respond to ready assertion or deassertion in time to satisfy the sink. A FIFO whose depth is equal to the difference in ready latency is inserted to compensate for the source’s inability to respond in time.