Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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6.1.2.2. Avalon® Memory Mapped Clock Crossing Bridge Parameters

Table 117.   Avalon® Memory Mapped Clock Crossing Bridge Parameters
Parameters Values Description
Data width 8, 16, 32, 64, 128, 256, 512, 1024 bits Determines the data width of the interfaces on the bridge, and affects the size of both FIFOs. For the highest bandwidth, set Data width to be as wide as the widest host that connects to the bridge.
Symbol width 1, 2, 4, 8, 16, 32, 64 (bits) Number of bits per symbol. For example, byte-oriented interfaces have 8-bit symbols.
Address width 1-32 bits The address bits needed to address the downstream agents.
Use automatically-determined address width - The minimum bridge address width that is required to address the downstream agents.
Maximum burst size 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 bits Determines the maximum length of bursts that the bridge supports.
Command FIFO depth

2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 bits

Command (host-to-agent) FIFO depth.
Respond FIFO depth

2, 4, 8,16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 bits

agent-to-host FIFO depth.
Master clock domain synchronizer depth 2, 3, 4, 5 bits The number of pipeline stages in the clock crossing logic in the issuing host to target agent direction. Increasing this value leads to a larger mean time between failures (MTBF). You can determine the MTBF for a design by running a timing analysis.
Slave clock domain synchronizer depth 2, 3, 4, 5 bits The number of pipeline stages in the clock crossing logic in the target agent to host direction. Increasing this value leads to a larger meantime between failures (MTBF). You can determine the MTBF for a design by running a timing analysis.