Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.7. Avalon® Streaming Round Robin Scheduler Intel® FPGA IP

The Avalon® Streaming Round Robin Scheduler Intel® FPGA IP controls the read operations from a multi-channel Avalon® streaming component that buffers data by channels. The IP reads the almost-full threshold values from the multiple channels in the multi-channel component, and then issues the read request to the Avalon® streaming source according to a round-robin scheduling algorithm.

Figure 232.  Avalon® Streaming Round Robin Scheduler Intel® FPGA IP

In a multi-channel component, the IP can store data either in the sequence that it comes in (FIFO), or in segments according to the channel. When data is stored in segments according to channels, a scheduler is needed to schedule the read operations.