Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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4.10.1.2. Expected Throughput Improvement

The throughput improvement that you can achieve with a pipelined read host is typically directly proportional to the pipeline depth of the interconnect and the agent interface. For example, if the total latency is two cycles, you can double the throughput by inserting a pipelined read host, assuming the agent interface also supports pipeline transfers. If either the host or agent does not support pipelined read transfers, then the interconnect asserts waitrequest until the transfer completes. You can also gain throughput when there are some cycles of overhead before a read response.

Where reads are not pipelined, the throughput is reduced. When both the host and agent interfaces support pipelined read transfers, data flows in a continuous stream after the initial latency. You can use a pipelined read host that stores data in a FIFO to implement a custom DMA, hardware accelerator, or off-chip communication interface.

Figure 144. Pipelined Read Host


This example shows a pipelined read host that stores data in a FIFO. The host performs word accesses that are word-aligned and reads from sequential memory addresses. The transfer length is a multiple of the word size.

When the go bit is asserted, the host registers the start_address and transfer_length signals. The host begins issuing reads continuously on the next clock cycle until the length register reaches zero. In this example, the word size is four bytes so that the address always increments by four, and the length decrements by four. The read signal remains asserted unless the FIFO fills to a predetermined level. The address register increments and the length register decrements if the length has not reached 0 and a read is posted.

The host posts a read transfer every time the read signal is asserted and the waitrequest is deasserted. The host issues reads until the entire buffer has been read or waitrequest is asserted. An optional tracking block monitors the done bit. When the length register reaches zero, some reads are outstanding. The tracking logic prevents assertion of done until the last read completes, and monitors the number of reads posted to the interconnect so that it does not exceed the space remaining in the readdata FIFO. This example includes a counter that verifies that the following conditions are met:

  • If a read is posted and readdatavalid is deasserted, the counter increments.
  • If a read is not posted and readdatavalid is asserted, the counter decrements.

When the length register and the tracking logic counter reach zero, all the reads have completed and the done bit is asserted. The done bit is important if a second host overwrites the memory locations that the pipelined read host accesses. This bit guarantees that the reads have completed before the original data is overwritten.