Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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6.5.1. Avalon® Streaming Splitter Intel® FPGA IP Backpressure

The Avalon® Streaming Splitter Intel® FPGA IP integrates with backpressure by AND-ing the ready signals from the output interfaces and sending the result to the input interface. As a result, if an output interface deasserts the ready signal, the input interface receives the deasserted ready signal, as well. This functionality ensures that backpressure on the output interfaces is propagated to the input interface.

When the Qualify Valid Out option is enabled, the out_valid signals on all other output interfaces are gated when backpressure is applied from one output interface. In this case, when any output interface deasserts its ready signal, the out_valid signals on the other output interfaces are also deasserted.

When the Qualify Valid Out option is disabled, the output interfaces have a non-gated out_valid signal when backpressure is applied. In this case, when an output interface deasserts its ready signal, the out_valid signals on the other output interfaces are not affected.

Because the logic is combinational, the Intel® FPGA IP introduces no latency.