Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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4.10.1. Avalon Pipelined Read Host Example

For a high throughput system using the Avalon® memory mapped standard, you can design a pipelined read host that allows a system to issue multiple read requests before data returns. Pipelined read hosts hide the latency of read operations by posting reads as frequently as every clock cycle. You can use this type of host when the address logic is not dependent on the data returning.