Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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4.7.2.2. Consolidating Interfaces

The following example shows a system with a mix of components, each having different burst capabilities: a Nios® II/e core, a Nios® II/f core, and an external processor, which off-loads some processing tasks to the Nios® II/f core.

The Nios® II/f core supports a maximum burst size of eight. The external processor interface supports a maximum burst length of 64. The Nios® II/e core does not support bursting. The memory in the system is SDRAM with an Avalon® maximum burst length of two.

Figure 133. Mixed Bursting System


Platform Designer automatically inserts burst adapters to compensate for burst length mismatches. The adapters reduce bursts to a single transfer, or the length of two transfers. For the external processor interface connecting to DDR SDRAM, a burst of 64 words is divided into 32 burst transfers, each with a burst length of two. When you generate a system, Platform Designer inserts burst adapters based on maximum burstcount values; consequently, the interconnect logic includes burst adapters between hosts and agent pairs that do not require bursting, if the host is capable of bursts.

In this example, Platform Designer inserts a burst adapter between the Nios® II processors and the timer, system ID, and PIO peripherals. These components do not support bursting and the Nios® II processor performs a single word read and write accesses to these components.

Figure 134. Mixed Bursting System with Bridges

To reduce the number of adapters, you can add pipeline bridges. The pipeline bridge, between the Nios® II/f core and the peripherals that do not support bursts, eliminates three burst adapters from the previous example. A second pipeline bridge between the Nios® II/f core and the DDR SDRAM, with its maximum burst size set to eight, eliminates another burst adapter, as shown below.