AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

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ID 683607
Date 8/24/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Intel® Quartus® Prime Software Guidelines 4. Device Guidelines 5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines
2. Overview x
2.1. Available Device Options and Ordering Part Numbers
3. Intel® Quartus® Prime Software Guidelines x
3.1. Design Migration 3.2. Intel® Quartus® Prime Software Patch Compatibility 3.3. Related Intel® Quartus® Prime Software Error Messages
4. Device Guidelines x
4.1. Device Configuration Guidelines 4.2. GPIO and LVDS Guidelines 4.3. Transceiver Guidelines 4.4. Error Message for Design Exceeding Maximum Transceiver Bandwidth
4.2. GPIO and LVDS Guidelines x
4.2.1. I/O Resource Comparison Between Standard OPN and IOL OPN Devices 4.2.2. Design Migration 4.2.3. Error Message for > 700 Pins Utilization
4.3. Transceiver Guidelines x
4.3.1. Transceiver Bandwidth Calculation
1. Introduction
2. Overview
3. Intel® Quartus® Prime Software Guidelines
4. Device Guidelines
5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

4.3. Transceiver Guidelines

Intel® Stratix® 10 I/O Limited (IOL) FPGAs have additional Intel® Quartus® Prime Fitter placement restrictions that set the maximum transceiver bandwidth at 499 Gbps for respective TX accumulative data rate and RX accumulative data rate across all used transceiver channels in a design.

Placement guidelines in the respective L/H/E/P-Tile Transceiver User Guide and in AN 778 apply for both standard Intel® Stratix® 10 and IOL Intel® Stratix® 10 FPGAs.

For related information, refer to:

L- and H-Tile Transceiver PHY User Guide

E-Tile Transceiver PHY User Guide

Intel FPGA P-Tile Avalon Streaming IP for PCI Express Design Example User Guide

P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

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