AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

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ID 683607
Date 8/24/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Intel® Quartus® Prime Software Guidelines 4. Device Guidelines 5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines
2. Overview x
2.1. Available Device Options and Ordering Part Numbers
3. Intel® Quartus® Prime Software Guidelines x
3.1. Design Migration 3.2. Intel® Quartus® Prime Software Patch Compatibility 3.3. Related Intel® Quartus® Prime Software Error Messages
4. Device Guidelines x
4.1. Device Configuration Guidelines 4.2. GPIO and LVDS Guidelines 4.3. Transceiver Guidelines 4.4. Error Message for Design Exceeding Maximum Transceiver Bandwidth
4.2. GPIO and LVDS Guidelines x
4.2.1. I/O Resource Comparison Between Standard OPN and IOL OPN Devices 4.2.2. Design Migration 4.2.3. Error Message for > 700 Pins Utilization
4.3. Transceiver Guidelines x
4.3.1. Transceiver Bandwidth Calculation
1. Introduction
2. Overview
3. Intel® Quartus® Prime Software Guidelines
4. Device Guidelines
5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

4.2.1. I/O Resource Comparison Between Standard OPN and IOL OPN Devices

The following table compares Intel® Stratix® 10 standard OPN and Intel® Stratix® 10 I/O Limited (IOL) OPN FPGAs.
Table 5.  Similarities and Difference Between Intel® Stratix® 10 Standard OPN and I/O Limited OPN FPGAs
Item Similarities Differences
I/O Feature I/O features are identical. (1) None
Pin Function All pin functions including power and configuration pins that are described in the Intel® Stratix® 10 device pin-out files are identical. (2) None
I/O Utilization Limit For F35 & F43 packages, the total I/O count utilization limits are identical between standard OPN and IOL OPN devices, because both have <700 I/O pins only.

For F50, F55 & F74 packages (3) the total I/O utilization is limited to a maximum of 700 pins for IOL OPNs.

The 700 I/O pins can be any pin combination listed within the pin-out file. For designs that utilize more than 700 pins in standard OPN devices, the total I/O count must be reduced to ≤700 to fit in the IOL device.
Note:
  1. Refer to Intel Stratix 10 General Purpose I/O User Guide for information on Intel® Stratix® 10 I/O features.
  2. Refer to Intel® Stratix® 10 Device Pin-Out Files.
  3. Intel® Stratix® 10 IOL FPGAs with F50, F55 & F74 package options are not available currently. For information, contact your Intel® representative.
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