AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

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ID 683607
Date 8/24/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Intel® Quartus® Prime Software Guidelines 4. Device Guidelines 5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines
2. Overview x
2.1. Available Device Options and Ordering Part Numbers
3. Intel® Quartus® Prime Software Guidelines x
3.1. Design Migration 3.2. Intel® Quartus® Prime Software Patch Compatibility 3.3. Related Intel® Quartus® Prime Software Error Messages
4. Device Guidelines x
4.1. Device Configuration Guidelines 4.2. GPIO and LVDS Guidelines 4.3. Transceiver Guidelines 4.4. Error Message for Design Exceeding Maximum Transceiver Bandwidth
4.2. GPIO and LVDS Guidelines x
4.2.1. I/O Resource Comparison Between Standard OPN and IOL OPN Devices 4.2.2. Design Migration 4.2.3. Error Message for > 700 Pins Utilization
4.3. Transceiver Guidelines x
4.3.1. Transceiver Bandwidth Calculation
1. Introduction
2. Overview
3. Intel® Quartus® Prime Software Guidelines
4. Device Guidelines
5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

4.4. Error Message for Design Exceeding Maximum Transceiver Bandwidth

When a design exceeds the maximum transceiver bandwidth of ≤499Gbps, the Intel® Quartus® Prime Fitter issues error messages during compilation. The system displays information relating to the error, immediately before the error message.

Information messages part 1 lists all the RX and TX channels and the data rate applied by the Fitter in transceiver bandwidth calculations, with one message line for each TX and RX channel. The message identifies whether the channel enables the transceiver dynamic reconfiguration feature. The following examples illustrate these information messages: 

RX Channel at PIN_<pin_number> is connected to the core and <reconfigurable/not reconfigurable>. The data-rate used is <data-rate> Gbps.
TX Channel at PIN_<pin_number> is connected to the core and <reconfigurable/not reconfigurable>. The data-rate used is <data-rate> Gbps.

Information messages part 2 lists the TX cumulative data rate and RX cumulative data rate that is applied by the Intel® Quartus® Prime software to determine whether transceiver bandwidth limit is exceeded. The following examples illustrate these information messages: 

TX cumulative data-rate of the current design is <data-rate Gbps>.
RX cumulative data-rate of the current design is <data-rate Gbps>.

An error message appears if the TX or RX cumulative data rate of the current design exceeds 499 Gbps. 

The current device <device OPN>’s data-rate cannot exceed 499Gbps. The design’s TX data-rate is <TX cumulative data-rate>, and RX data-rate is <RX cumulative data-rate>.

The following figures show examples of Intel® Quartus® Prime software information messages and error messages for the following data rates, respectively:

  • TX and RX cumulative data rate of 498.998400 Gbps
  • TX and RX cumulative data rate of 499.200000 Gbps
  • TX and RX cumulative data rate of 1184.00000 Gbps
Figure 10. Example of Intel® Quartus® Prime Software Information Messages with TX and RX Cumulative Data Rate of 498.998400 Gbps, with Transceiver Dynamic Reconfiguration Disabled

Figure 11. Example of Intel® Quartus® Prime Software Information and Error Messages with TX and RX Cumulative Data Rate of 499.200000 Gbps, with Transceiver Dynamic Reconfiguration Disabled

Figure 12. Example of Intel® Quartus® Prime Software Information and Error Messages With TX and RX Cumulative Data Rate of 1184.00000 Gbps, with Transceiver Dynamic Reconfiguration Enabled
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