AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

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ID 683607
Date 8/24/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Intel® Quartus® Prime Software Guidelines 4. Device Guidelines 5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines
2. Overview x
2.1. Available Device Options and Ordering Part Numbers
3. Intel® Quartus® Prime Software Guidelines x
3.1. Design Migration 3.2. Intel® Quartus® Prime Software Patch Compatibility 3.3. Related Intel® Quartus® Prime Software Error Messages
4. Device Guidelines x
4.1. Device Configuration Guidelines 4.2. GPIO and LVDS Guidelines 4.3. Transceiver Guidelines 4.4. Error Message for Design Exceeding Maximum Transceiver Bandwidth
4.2. GPIO and LVDS Guidelines x
4.2.1. I/O Resource Comparison Between Standard OPN and IOL OPN Devices 4.2.2. Design Migration 4.2.3. Error Message for > 700 Pins Utilization
4.3. Transceiver Guidelines x
4.3.1. Transceiver Bandwidth Calculation
1. Introduction
2. Overview
3. Intel® Quartus® Prime Software Guidelines
4. Device Guidelines
5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

2. Overview

Intel® Stratix® 10 I/O Limited (IOL) FPGAs are designated with ordering part numbers (OPN) that end with an -NL suffix.

The Intel® Quartus® Prime software has restrictions on Intel® Stratix® 10 IOL FPGAs to limit GPIO, LVDS, and transceiver utilization.

The following table shows feature support for Intel® Stratix® 10 IOL FPGAs and Intel® Stratix® 10 standard OPN FPGAs.

Table 1.   Intel® Stratix® 10 I/O Limited Device and Intel® Stratix® 10 Standard Device Feature Comparison
Feature Parameter Standard Device I/O Limited Device
Configuration Scheme Support all schemes with no functionality or performance difference.
Programming file compatibility (1) (1)
GPIO and LVDS Maximum I/O pin count utilization (2) (3) >700 pins (4) ≤700 pins
Transceiver Maximum bandwidth utilization (5) >499 Gbps ≤499 Gbps
Dynamic reconfiguration Yes Yes (6)
Note:
  1. Refer to the Device Configuration Guidelines topic for details.
  2. GPIO and LVDS pin counts are limited to 700 pins by the Intel® Quartus® Prime software IOL restriction. LVDS pin count is 2 pins per pair.
  3. The I/O pin count includes general purpose I/O, LVDS I/O, and high voltage I/O.
  4. Maximum I/O pin count availability depends on device package selection.
  5. For details of the Intel® Quartus® Prime software bandwidth calculation, refer to the Transceiver Bandwidth Calculation topic.
  6. Enabling Dynamic Reconfiguration reduces transceiver maximum bandwidth per Intel® Quartus® Prime software IOL restrictions. Refer to the Dynamic Reconfiguration Status section in the Transceiver Bandwidth Calculation topic for more information.
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