AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

ID 683607
Date 8/24/2021
Public

4.3.1. Transceiver Bandwidth Calculation

The transceiver data rate for each channel that is applied to the design's TX cumulative data rate and RX cumulative data rate is subject to two native PHY IP configurations: signal modulation mode, and dynamic reconfiguration status.

Signal Modulation Mode

By default, the native PHY IP applies non-return-to-zero (NRZ) modulation for electrical signaling unless you select Pulse-Amplitude Modulation 4-Level (PAM4) in E-Tile. L-Tile and H-Tile have NRZ modulation for electrical signaling only.

When a channel uses NRZ, the data rate value counts as a single channel; however, when a link uses PAM4, the data rate value counts as two channels when it uses two physical channels.

Example of the calculation for a use model with one channel of 10 Gbps using NRZ and one link 56 Gbps using PAM4 signaling:

Bandwidth = (10Gbps x 1 channel) + (56 Gbps x 2 channels) = 122 Gbps

Dynamic Reconfiguration Status

For L-Tile, H-Tile, and E-Tile devices, the data rate used by the Intel® Quartus® Prime software for TX and RX data rate is subject to the status of the transceiver dynamic reconfiguration feature.

When you have not enabled dynamic reconfiguration, the data rate is defined by the data rate attribute set in the native PHY IP. When you have enabled dynamic reconfiguration, the data rate is defined by the maximum data rate of the channel per the fastest transceiver specification of the L-Tile, H-Tile, or E-Tile.

Transceiver bandwidth is further reduced according to the following definitions:

  • For L-Tile devices, the Intel® Quartus® Prime software applies the maximum data rate of the channel at transceiver speed grade 2, because L-Tile does not have transceiver speed grade 1.
  • For H-Tile and E-Tile devices, the Intel® Quartus® Prime software applies the maximum data rate of the channel at transceiver speed grade 1, even though the I/O Limited (IOL) OPN transceiver speed grade is 2.

The following table illustrates an example that uses 10 Gbps across all channels, within an L-Tile, H-Tile, or E-Tile device.

Table 6.  Effective Data Rate per Channel for Intel® Quartus® Prime Software Transceiver Bandwidth Calculation with Example of 10Gbps Native PHY IP
Dynamic Reconfiguration Status
Disable Enable
Channel Location Applied Data Rate per Channel (Gbps) Channel Location Applied Data Rate per Channel (Gbps)
L-Tile H-Tile E-Tile (NRZ/PAM4) L-Tile H-Tile E-Tile (NRZ/PAM4)
23 10 10 10 / 20 23 17.4 17.4 28.9 / 57.4
22 10 10 10 / 20 22 26.6 28.3 28.9 / 57.4
21 10 10 10 / 20 21 26.6 28.3 28.9 / 57.4
20 10 10 10 / 20 20 17.4 17.4 28.9 / 57.4
19 10 10 10 / 20 19 26.6 28.3 28.9 / 57.4
18 10 10 10 / 20 18 26.6 28.3 28.9 / 57.4
17 10 10 10 / 20 17 17.4 17.4 28.9 / 57.4
16 10 10 10 / 20 16 26.6 28.3 28.9 / 57.4
15 10 10 10 / 20 15 26.6 28.3 28.9 / 57.4
14 10 10 10 / 20 14 17.4 17.4 28.9 / 57.4
13 10 10 10 / 20 13 26.6 28.3 28.9 / 57.4
12 10 10 10 / 20 12 26.6 28.3 28.9 / 57.4
11 10 10 10 / 20 11 17.4 17.4 28.9 / 57.4
10 10 10 10 / 20 10 26.6 28.3 28.9 / 57.4
9 10 10 10 / 20 9 26.6 28.3 28.9 / 57.4
8 10 10 10 / 20 8 17.4 17.4 28.9 / 57.4
7 10 10 10 / 20 7 26.6 28.3 28.9 / 57.4
6 10 10 10 / 20 6 26.6 28.3 28.9 / 57.4
5 10 10 10 / 20 5 17.4 17.4 28.9 / 57.4
4 10 10 10 / 20 4 26.6 28.3 28.9 / 57.4
3 10 10 10 / 20 3 26.6 28.3 28.9 / 57.4
2 10 10 10 / 20 2 17.4 17.4 28.9 / 57.4
1 10 10 10 / 20 1 26.6 28.3 28.9 / 57.4
0 10 10 10 / 20 0 26.6 28.3 28.9 / 57.4