Intel Stratix 10 General Purpose I/O User Guide
Version Information
Updated for: |
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Intel® Quartus® Prime Design Suite 20.3 |
1. Intel Stratix 10 I/O Overview
- The IOEs contain bidirectional I/O buffers and I/O registers located in LVDS I/O banks.
- The GPIO IP core supports the GPIO components and features, including double data rate I/O (DDIO), delay chains, I/O buffers, control signals, and clocking.
- Two of the LVDS I/O banks are shared with the Secure Device Manager (SDM).
- For devices with Hard Processor System (HPS), three of the LVDS I/O banks are shared with the HPS SDRAM interface.
- The 3 V I/O banks do not feature I/O registers and DDIOs.
- The 3.3 V I/O bank is available in the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices.
1.1. Intel Stratix 10 I/O and Differential I/O Buffers
The general purpose I/Os (GPIOs) consist of the following I/O banks:
- LVDS I/O bank—supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination between the two pins. You can use each LVDS channel as transmitter only or receiver only. Each LVDS channel supports transmit SERDES and receive SERDES with DPA circuitry. For example, if you use 30 channels of the available 72 channels as transmitters, you can use the remaining 42 channels as receivers.
-
3 V I/O bank—supports single-ended LVCMOS and LVTTL I/O standards up to 3.0 V. In
Intel®
Stratix® 10 devices, each 3 V I/O bank supports only two output enables (OE) for its eight single-ended I/Os. Single-ended I/Os within this I/O bank support all programmable I/O element (IOE) features except:
- Programmable pre-emphasis
- RD on-chip termination (OCT)
- Calibrated RS and RT OCT
- Internal VREF generation
- Dynamic OCT
-
3.3 V I/O bank—supports single-ended LVCMOS and LVTTL I/O standards at 3.3 V and 3.0 V. This feature is available only in the HF35 package of the
Intel®
Stratix® 10
GX 400 and SX 400 devices. The 3.3 V I/O buffer is unidirectional. You can configure the I/O pins in the bank in preset groups of eight pins—as all input pins or all output pins. The bank supports the following features:
- As input—programmable pull up resistor
- As output—programmable current strength
1.2. Intel Stratix 10 I/O Migration Support
- In the following figures, the arrows indicate the migration paths. The devices included in each migration path are shaded.
- If the line connects two different columns, you can migrate between different packages of the product lines. However, different ordering part number of the product lines may have different LE count, transceiver count, or HBM features.
- To achieve the full I/O migration across product lines in the same migration path, restrict I/Os and transceivers usage to match the product line with the lowest I/O and transceiver counts.
2. Intel Stratix 10 I/O Architecture and Features
The Intel® Stratix® 10 I/Os support the following features:
- Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
- Low-voltage differential signaling (LVDS), RSDS, mini-LVDS, HSTL, HSUL, SSTL, and POD I/O standards
- Serializer/deserializer (SERDES)
- Programmable output current strength
- Programmable slew rate
- Programmable bus-hold
- Programmable weak pull-up resistor
- Programmable pre-emphasis for DDR4 and the LVDS output buffer
- Programmable I/O delay
- Programmable differential output voltage (VOD)
- Programmable open-drain output
- On-chip series termination (RS OCT) with and without calibration
- On-chip parallel termination (RT OCT)
- On-chip differential termination (RD OCT)
- HSTL and SSTL input buffer with dynamic power down
- Dynamic on-chip parallel termination for all I/O banks
- Internally generated VREF with DDR4 calibration
2.1. I/O Standards and Voltage Levels in Intel Stratix 10 Devices
2.1.1. Intel Stratix 10 I/O Standards Support
I/O Standard | I/O Buffer Type Support | Application | Standard Support | ||
---|---|---|---|---|---|
LVDS I/O | 3 V I/O1 2 | 3.3 V I/O3 | |||
3.3 V LVTTL/3.3 V LVCMOS | No | No | Yes | General purpose | JESD8-B |
3.0 V LVTTL/3.0 V LVCMOS | No | Yes 4 | Yes | General purpose | JESD8-B |
2.5 V LVCMOS | No | Yes 5 | No | General purpose | JESD8-5 |
1.8 V LVCMOS | Yes | Yes 5 | No | General purpose | JESD8-7 |
1.5 V LVCMOS | Yes | Yes 5 | No | General purpose | JESD8-11 |
1.2 V LVCMOS | Yes | Yes 5 | No | General purpose | JESD8-12 |
SSTL-18 Class I and Class II | Yes | No | No | Flash interface | JESD8-15 |
SSTL-15 Class I and Class II | Yes | No | No | DDR3 | — |
SSTL-15 | Yes | No | No | DDR3 | JESD79-3D |
SSTL-135 | Yes | No | No | DDR3L | — |
SSTL-125 6 | Yes | No | No | QDR-IV | — |
SSTL-12 | Yes | No | No | RLDRAM 3, QDR-IV | — |
POD12 | Yes | No | No | DDR4, QDR-IV | JESD8-24 |
1.8 V HSTL Class I and Class II | Yes | No | No | DDR II+, QDR II+, and RLDRAM 2 | JESD8-6 |
1.5 V HSTL Class I and Class II | Yes | No | No | DDR II+, QDR II+, QDR II, and RLDRAM 2 | JESD8-6 |
1.2 V HSTL Class I and Class II | Yes | No | No | QDR-IV, General purpose | JESD8-16A |
HSUL-12 | Yes | No | No | LPDDR2, LPDDR3 | — |
Differential SSTL-18 Class I and Class II | Yes | No | No | General purpose | JESD8-15 |
Differential SSTL-15 Class I and Class II | Yes | No | No | DDR3 | — |
Differential SSTL-15 | Yes | No | No | DDR3 | JESD79-3D |
Differential SSTL-135 | Yes | No | No | DDR3L | — |
Differential SSTL-1256 | Yes | No | No | General purpose | — |
Differential SSTL-12 | Yes | No | No | RLDRAM 3 | — |
Differential POD12 | Yes | No | No | DDR4 | JESD8-24 |
Differential 1.8 V HSTL Class I and Class II | Yes | No | No | DDR II+, QDR II+, and RLDRAM 2 | JESD8-6 |
Differential 1.5 V HSTL Class I and Class II | Yes | No | No | DDR II+, QDR II+, QDR II, and RLDRAM 2 | JESD8-6 |
Differential 1.2 V HSTL Class I and Class II | Yes | No | No | General purpose | JESD8-16A |
Differential HSUL-12 | Yes | No | No | LPDDR2, LPDDR3 | — |
LVDS 7 | Yes | No | No | SGMII, SFI, SPI | ANSI/TIA/EIA-644 |
Mini-LVDS 7 | Yes | No | No | SGMII, SFI, SPI | — |
RSDS7 | Yes | No | No | SGMII, SFI, SPI | — |
LVPECL | Yes | No | No | SGMII, SFI, SPI | — |
I/O Standard | Application | Standard Support |
---|---|---|
1.8 V LVCMOS | General purpose | JESD8-7 |
2.1.2. Intel Stratix 10 I/O Standards Voltage Support
- The I/O buffers are powered by VCC, VCCPT and VCCIO.
- Each I/O bank has its own VCCIO supply and supports only one VCCIO voltage.
- In all LVDS I/O banks, you can use any of the listed VCCIO voltages except 2.5 V, 3.0 V, and 3.3 V. However, LVDS I/O bank 3D of the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices supports only 1.8 V VCCIO.
- The 2.5 V and 3.0 V VCCIO voltages are supported only on the 3 V I/O banks.
- The 3.3 V VCCIO voltages are supported only on I/O bank 3C of the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices. I/O bank 3C of these devices also supports 3.0 V.
- For the maximum and minimum input voltages allowed, refer to the device datasheet.
I/O Standard | VCCIO(V) |
VCCPT(V) (Pre-Driver Voltage) |
VREF(V) (Input Ref Voltage) |
VTT(V) (Board Termination Voltage) |
|
---|---|---|---|---|---|
Input8 | Output | ||||
3.3 V LVTTL/3.3 V LVCMOS 9 | 3.3 | 3.3 | 1.8 | — | — |
3.0 V LVTTL/3.0 V LVCMOS | 3.0 | 3.0 | 1.8 | — | — |
2.5 V LVCMOS | 3.0/2.5 | 2.5 | 1.8 | — | — |
1.8 V LVCMOS | 1.8 | 1.8 | 1.8 | — | — |
1.5 V LVCMOS | 1.5 | 1.5 | 1.8 | — | — |
1.2 V LVCMOS | 1.2 | 1.2 | 1.8 | — | — |
SSTL-18 Class I and Class II | VCCPT | 1.8 | 1.8 | 0.9 | 0.9 |
SSTL-15 Class I and Class II | VCCPT | 1.5 | 1.8 | 0.75 | 0.75 |
SSTL-15 | VCCPT | 1.5 | 1.8 | 0.75 | 0.75 |
SSTL-135 | VCCPT | 1.35 | 1.8 | 0.675 | 0.675 |
SSTL-125 | VCCPT | 1.25 | 1.8 | 0.625 | 0.625 |
SSTL-12 | VCCPT | 1.2 | 1.8 | 0.6 | 0.6 |
POD12 | VCCPT | 1.2 | 1.8 | 0.84 | 1.2 |
1.8 V HSTL Class I and Class II | VCCPT | 1.8 | 1.8 | 0.9 | 0.9 |
1.5 V HSTL Class I and Class II | VCCPT | 1.5 | 1.8 | 0.75 | 0.75 |
1.2 V HSTL Class I and Class II | VCCPT | 1.2 | 1.8 | 0.6 | 0.6 |
HSUL-12 | VCCPT | 1.2 | 1.8 | 0.6 | — |
Differential SSTL-18 Class I and Class II | VCCPT | 1.8 | 1.8 | — | 0.9 |
Differential SSTL-15 Class I and Class II | VCCPT | 1.5 | 1.8 | — | 0.75 |
Differential SSTL-15 | VCCPT | 1.5 | 1.8 | — | 0.75 |
Differential SSTL-135 | VCCPT | 1.35 | 1.8 | — | 0.675 |
Differential SSTL-125 | VCCPT | 1.25 | 1.8 | — | 0.625 |
Differential SSTL-12 | VCCPT | 1.2 | 1.8 | — | 0.6 |
Differential POD12 | VCCPT | 1.2 | 1.8 | — | 1.2 |
Differential 1.8 V HSTL Class I and Class II | VCCPT | 1.8 | 1.8 | — | 0.9 |
Differential 1.5 V HSTL Class I and Class II | VCCPT | 1.5 | 1.8 | — | 0.75 |
Differential 1.2 V HSTL Class I and Class II | VCCPT | 1.2 | 1.8 | — | 0.6 |
Differential HSUL-12 | VCCPT | 1.2 | 1.8 | — | — |
LVDS 10 | VCCPT | 1.8 | 1.8 | — | — |
Mini-LVDS 10 | VCCPT | 1.8 | 1.8 | — | — |
RSDS10 | VCCPT | 1.8 | 1.8 | — | — |
LVPECL (Differential clock input only) | VCCPT | — | 1.8 | — | — |
2.2. I/O Element Structure in Intel Stratix 10 Devices
The I/O elements (IOEs) in Intel® Stratix® 10 devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.
The IOEs are located in I/O columns within the core fabric of the Intel® Stratix® 10 device.
Intel® Stratix® 10 SX devices also have IOEs for the HPS.
The GPIO IOE register consists of the DDR register, the half rate register, and the transmitter delay chains for input, output, and output enable (OE) paths:
- You can take data from the combinatorial path or the registered path.
- Only the core clock clocks the data.
- The half rate clock routed from the core clocks the half rate register.
- The full rate clock from the core clocks the full rate register.
2.2.1. I/O Bank Architecture in Intel Stratix 10 Devices
However, the DPA block and SERDES are not available in the following I/O banks in package HF35 of the following devices:
- Intel® Stratix® 10 GX 400 and SX 400 devices—I/O banks 3A, 3C, and 3D
- Intel® Stratix® 10 TX 400 devices—I/O banks 3A and 3D
In each 3 V or 3.3 V I/O bank, there are eight single-ended I/O buffers. The 3.3 V I/O bank in package HF35 of the Intel® Stratix® 10 GX 400 and SX 400 devices supports only unidirectional single-ended 3.3 V or 3.0 V I/O buffers. In the 3.3 V I/O bank, the pins form eight-pin groups. You can configure all eight pins in a group together as all input only or all output only. To identify the pin groups, refer to the Optional Function(s) column in device pin out files.
2.2.2. I/O Buffer and Registers in Intel Stratix 10 Devices
I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to the output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization. Use the GPIO Intel® FPGA IP to utilize these registers to implement DDR circuitry.
The input and output paths contain the following blocks:
- Input registers—support half or full rate data transfer from peripheral to core, and support double or single data rate data capture from I/O buffer.
- Output registers—support half or full rate data transfer from core to peripheral, and support double or single data rate data transfer to I/O buffer.
- OE registers—support half or full rate data transfer from core to peripheral, and support single data rate data transfer to I/O buffer.
The input and output paths also support the following features:
- Clock enable.
- Asynchronous or synchronous reset.
- Bypass mode for input and output paths.
- Delays chains on input and output paths.
2.3. Programmable IOE Features in Intel Stratix 10 Devices
Feature |
Setting |
Condition |
Intel® Quartus® Prime Assignment Name |
---|---|---|---|
Slew Rate Control | 0 (Slow), 1 (Fast). Default is 1. | Disabled if you use the RS OCT feature. | SLEW_RATE |
I/O Delay | Refer to the device datasheet | — |
INPUT_DELAY_CHAIN OUTPUT_DELAY_CHAIN |
Open-Drain Output | On, Off. Default is Off | — | AUTO_OPEN_DRAIN_PINS |
Bus-Hold | On, Off. Default is Off. | Disabled if you use the weak pull-up resistor feature. | ENABLE_BUS_HOLD_CIRCUITRY |
Weak Pull-up Resistor | On, Off. Default is Off. | Disabled if you use the bus-hold feature. | WEAK_PULL_UP_RESISTOR |
Pre-Emphasis | 0 (disabled), 1 (enabled). Default is 1. | — | PROGRAMMABLE_PREEMPHASIS |
Differential Output Voltage | 0 (low), 1 (medium low), 2 (medium high), 3 (high). Default is 2. | — | PROGRAMMABLE_VOD |
Feature | I/O Buffer Type Support |
I/O Standards Support |
||
---|---|---|---|---|
LVDS I/O | 3 V I/O |
HPS I/O (SoC Devices Only) |
||
Slew Rate Control 11 | Yes | Yes | Yes |
|
I/O Delay | Yes | Yes | — | |
Open-Drain Output11 | Yes | Yes | Yes |
|
Bus-Hold11 | Yes | Yes | — | |
Weak Pull-up Resistor11 | Yes | Yes | Yes | |
Pre-Emphasis | Yes | — | — |
|
Differential Output Voltage | Yes | — | — |
|
2.3.1. Programmable Output Slew Rate Control
You can select between two slew rate settings, 1 and 0:
- Fast slew rate (1)—provides high-speed transitions for high-performance systems. This is the default setting. If you enable on-chip termination (OCT), this setting is always used.
- Slow slew rate (0)—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.
2.3.2. Programmable IOE Delay
To ensure that the signals within a bus have the same delay going into or out of the device, each pin can have different delay values:
- Delay from input pin to input register
- Delay from output pin to output register
For more information about the programmable IOE delay specifications, refer to the device datasheet.
2.3.3. Programmable Open-Drain Output
You can attach several open-drain outputs to a wire. This connection type is like a logical OR function and is commonly called an active-low wired-OR circuit. If at least one of the outputs is in logic 0 state (active), the circuit sinks the current and brings the line to low voltage.
You can use open-drain output if you are connecting multiple devices to a bus. For example, you can use the open-drain output for system-level control signals that can be asserted by any device or as an interrupt.
- Design the tristate buffer using OPNDRN primitive.
- Turn on the Auto Open-Drain Pins option in the Intel® Quartus® Prime software.
2.3.4. Programmable Bus Hold
The bus-hold circuitry uses a resistor with a nominal resistance (RBH), approximately 7 kΩ, to weakly pull the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.
For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the VCCIO level.
If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the I/O pin for differential signals, disable the bus-hold feature.
2.3.5. Programmable Pull-Up Resistor
The Intel® Stratix® 10 device supports programmable weak pull-up resistors only on user I/O pins but not on dedicated configuration pins, dedicated clock pins, or JTAG pins.
If you enable the weak pull-up resistor, you cannot use the bus-hold feature.
2.3.6. Programmable Pre-Emphasis
The VOD setting and the output impedance of the driver set the output current limit of a high-speed transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full VOD level before the next edge, producing pattern-dependent jitter. With pre-emphasis, the output current is boosted momentarily during switching to increase the output slew rate.
Pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line. The overshoot introduced by the extra current happens only during a change of state switching to increase the output slew rate and does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.
Field | Assignment |
---|---|
To | tx_out |
Assignment name | Programmable Pre-emphasis |
Allowed values | 0 (disabled), 1 (enabled). Default is 1. |
2.3.7. Programmable Differential Output Voltage
The programmable VOD settings allow you to adjust the output eye opening to optimize the trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end, and a smaller VOD swing reduces power consumption. You can statically adjust the VOD of the differential signal by changing the VOD settings in the Intel® Quartus® Prime software Assignment Editor.
Field | Assignment |
---|---|
To | tx_out |
Assignment name | Programmable Differential Output Voltage (VOD) |
Allowed values | 0 (low), 1 (medium low), 2 (medium high), 3 (high). Default is 2. |
2.3.8. Programmable Current Strength
To use programmable current strength, you must specify the current strength assignment in the Intel® Quartus® Prime software. Without explicit assignments, the Intel® Quartus® Prime software uses these predefined default values:
- All HSTL and SSTL Class I, and all non-voltage-referenced I/O standards—50 Ω RS OCT without calibration
- All HSTL and SSTL Class II I/O standards—25 Ω RS OCT without calibration
- POD12 I/O standard—34 Ω RS OCT without calibration
I/O Standard |
IOH / IOL Current Strength Setting (mA) |
||||
---|---|---|---|---|---|
Supported in FPGA |
Supported in HPS 12 (SoC Devices Only) |
||||
Available | Default | Available | Default | ||
3.3 V LVTTL 13 | 12, 8, 4 | 12 | — | — | |
3.3 V LVCMOS13 | 12, 8, 4 | 12 | — | — | |
3.0 V LVTTL | 3.3 V I/O bank13 | 12, 8, 4 | 12 | — | — |
3 V I/O bank 14 | 24, 20, 16, 12, 8, 4 | ||||
3.0 V LVCMOS | 3.3 V I/O bank13 | 12, 8, 4 | 12 | — | — |
3 V I/O bank14 | 24, 20, 16, 12, 8, 4 | ||||
2.5 V LVCMOS | 16, 12, 8, 4 | 12 | — | — | |
1.8 V LVCMOS | 16, 12, 10, 8, 6, 4, 2 | 12 | 12, 10, 8 | 12 | |
1.5 V LVCMOS | 12, 10, 8, 6, 4, 2 | 12 | — | — | |
1.2 V LVCMOS | 8, 6, 4, 2 | 8 | — | — | |
SSTL-18 Class I | 8, 6, 4 | 8 | — | — | |
SSTL-18 Class II | 8 | 8 | — | — | |
SSTL-15 Class I | 8, 6, 4 | 8 | — | — | |
SSTL-15 Class II | 8 | 8 | — | — | |
SSTL-135 | 8, 6, 4 | 8 | — | — | |
SSTL-125 | 8, 6, 4 | 8 | — | — | |
SSTL-12 | 8, 6, 4 | 8 | — | — | |
POD12 | 8, 6, 4 | 8 | — | — | |
1.8 V HSTL Class I | 12, 10, 8, 6, 4 | 8 | — | — | |
1.8 V HSTL Class II | 14 | 14 | — | — | |
1.5 V HSTL Class I | 12, 10, 8, 6, 4 | 8 | — | — | |
1.5 V HSTL Class II | 14 | 14 | — | — | |
1.2 V HSTL Class I | 8, 6, 4 | 8 | — | — | |
Differential SSTL-18 Class I | 8, 6, 4 | 8 | — | — | |
Differential SSTL-18 Class II | 8 | 8 | — | — | |
Differential SSTL-15 Class I | 8, 6, 4 | 8 | — | — | |
Differential SSTL-15 Class II | 8 | 8 | — | — | |
Differential SSTL-135 | 12, 10, 8, 6, 4 | 8 | — | — | |
Differential SSTL-125 | 12, 10, 8, 6, 4 | 8 | — | — | |
Differential SSTL-12 Class I | 12, 10, 8, 6, 4 | 8 | — | — | |
Differential POD12 | 8, 6, 4 | 8 | — | — | |
Differential 1.8 V HSTL Class I | 12, 10, 8, 6, 4 | 8 | — | — | |
Differential 1.8 V HSTL Class II | 14 | 14 | — | — | |
Differential 1.5 V HSTL Class I | 12, 10, 8, 6, 4 | 8 | — | — | |
Differential 1.5 V HSTL Class II | 14 | 14 | — | — | |
Differential 1.2 V HSTL Class I | 8, 6, 4 | 8 | — | — |
2.4. On-Chip I/O Termination in Intel Stratix 10 Devices
Serial (RS) and parallel (RT) OCT provides I/O impedance matching and termination capabilities. OCT maintains signal quality, saves board space, and reduces external component costs.
- The 3 V I/Os support only OCT without calibration.
- The 3.3 V I/Os do not support OCT.
Direction | OCT Schemes | I/O Type Support | ||
---|---|---|---|---|
LVDS I/O | 3 V I/O | 3.3 V I/O | ||
Output | RS OCT with calibration | Yes | — | — |
RS OCT without calibration | Yes | Yes | — | |
Input | RT OCT with calibration | Yes | — | — |
RD OCT (LVDS I/O standard only) | Yes | — | — | |
Bidirectional | Dynamic RS and RT OCT | Yes | — | — |
2.4.1. RS OCT without Calibration in Intel Stratix 10 Devices
Intel® Stratix® 10 devices support RS OCT for single-ended and voltage-referenced I/O standards. RS OCT without calibration is supported on output only.
I/O Standard | Uncalibrated OCT (Output) |
---|---|
RS (Ω) | |
3.0 V LVTTL/3.0 V LVCMOS | 25, 50 |
2.5 V LVCMOS | 25, 50 |
1.8 V LVCMOS | 25, 50 |
1.5 V LVCMOS | 25, 50 |
1.2 V LVCMOS | 25, 50 |
SSTL-18 Class I | 50 |
SSTL-18 Class II | 25 |
SSTL-15 Class I | 50 |
SSTL-15 Class II | 25 |
SSTL-15 | 34, 40 |
SSTL-135 | 34, 40 |
SSTL-125 | 34, 40 |
SSTL-12 | 34, 40, 60, 120, 240 |
POD12 | 34, 40, 48, 60 |
1.8 V HSTL Class I | 50 |
1.8 V HSTL Class II | 25 |
1.5 V HSTL Class I | 50 |
1.5 V HSTL Class II | 25 |
1.2 V HSTL Class I | 50 |
1.2 V HSTL Class II | 25 |
HSUL-12 | 34, 40, 48, 60, 80 |
Differential SSTL-18 Class I | 50 |
Differential SSTL-18 Class II | 25 |
Differential SSTL-15 Class I | 50 |
Differential SSTL-15 Class II | 25 |
Differential SSTL-15 | 34, 40 |
Differential SSTL-15 Class I | 50 |
Differential SSTL-15 Class II | 25 |
Differential SSTL-135 | 34, 40 |
Differential SSTL-125 | 34, 40 |
Differential SSTL-12 | 34, 40, 60, 120, 240 |
Differential POD12 | 34, 40, 48, 60 |
Differential 1.8 V HSTL Class I | 50 |
Differential 1.8 V HSTL Class II | 25 |
Differential 1.5 V HSTL Class I | 50 |
Differential 1.5 V HSTL Class II | 25 |
Differential 1.2 V HSTL Class I | 50 |
Differential 1.2 V HSTL Class II | 25 |
Differential HSUL-12 | 34, 40, 48, 60, 80 |
Driver-impedance matching provides the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, you can significantly reduce signal reflections on PCB traces.
If you use impedance matching, you cannot specify the current strength.
2.4.2. RS OCT with Calibration in Intel Stratix 10 Devices
The Intel® Stratix® 10 devices support RS OCT with calibration in all LVDS I/O banks.
I/O Standard | Calibrated OCT (Output) | |
---|---|---|
RS (Ω) | RZQ (Ω) | |
1.8 V LVCMOS | 25, 50 | 100 |
1.5 V LVCMOS | 25, 50 | 100 |
1.2 V LVCMOS | 25, 50 | 100 |
SSTL-18 Class I | 50 | 100 |
SSTL-18 Class II | 25 | 100 |
SSTL-15 Class I | 50 | 100 |
SSTL-15 Class II | 25 | 100 |
SSTL-15 | 34, 40 | 240 |
SSTL-135 | 34, 40 | 240 |
SSTL-125 | 34, 40 | 240 |
SSTL-12 | 34, 40, 60, 120, 240 | 240 |
POD12 | 34, 40, 48, 60 | 240 |
1.8 V HSTL Class I | 50 | 100 |
1.8 V HSTL Class II | 25 | 100 |
1.5 V HSTL Class I | 50 | 100 |
1.5 V HSTL Class II | 25 | 100 |
1.2 V HSTL Class I | 50 | 100 |
1.2 V HSTL Class II | 25 | 100 |
HSUL-12 | 34, 40, 48, 60, 80 | 240 |
Differential SSTL-18 Class I | 50 | 100 |
Differential SSTL-18 Class II | 25 | 100 |
Differential SSTL-15 Class I | 50 | 100 |
Differential SSTL-15 Class II | 25 | 100 |
Differential SSTL-15 | 34, 40 | 240 |
Differential SSTL-135 | 34, 40 | 240 |
Differential SSTL-15 Class I | 50 | 100 |
Differential SSTL-15 Class II | 25 | 100 |
Differential SSTL-125 | 34, 40 | 240 |
Differential SSTL-12 | 34, 40, 60, 120, 240 | 240 |
Differential POD12 | 34, 40, 48, 60 | 240 |
Differential 1.8 V HSTL Class I | 50 | 100 |
Differential 1.8 V HSTL Class II | 25 | 100 |
Differential 1.5 V HSTL Class I | 50 | 100 |
Differential 1.5 V HSTL Class II | 25 | 100 |
Differential 1.2 V HSTL Class I | 50 | 100 |
Differential 1.2 V HSTL Class II | 25 | 100 |
Differential HSUL-12 | 34, 40, 48, 60, 80 | 240 |
The RS OCT calibration circuit compares the total impedance of the I/O buffer to the external reference resistor connected to the RZQ pin and dynamically enables or disables the transistors until they match.
Calibration occurs at the end of device configuration. When the calibration circuit finds the correct impedance, the circuit powers down and stops changing the characteristics of the drivers.
2.4.3. RT OCT with Calibration in Intel Stratix 10 Devices
The Intel® Stratix® 10 devices support RT OCT with calibration in all LVDS I/O banks but not in the 3 V I/O banks. RT OCT with calibration is available only for configuration of input and bidirectional pins. Output pin configurations do not support RT OCT with calibration. If you use RT OCT, the VCCIO of the bank must match the I/O standard of the pin where you enable the RT OCT.
I/O Standard | Calibrated OCT (Input) | |
---|---|---|
RT (Ω) | RZQ (Ω) | |
SSTL-18 Class I | 50 | 100 |
SSTL-18 Class II | 50 | 100 |
SSTL-15 Class I | 50 | 100 |
SSTL-15 Class II | 50 | 100 |
SSTL-15 | 48, 60,120 | 240 |
SSTL-135 | 48, 60, 120 | 240 |
SSTL-125 | 48, 60, 120 | 240 |
SSTL-12 | 60, 120 | 240 |
POD12 | 34, 40, 48, 60, 80, 120, 240 | 240 |
1.8 V HSTL Class I | 50 | 100 |
1.8 V HSTL Class II | 50 | 100 |
1.5 V HSTL Class I | 50 | 100 |
1.5 V HSTL Class II | 50 | 100 |
1.2 V HSTL Class I | 50 | 100 |
1.2 V HSTL Class II | 50 | 100 |
Differential SSTL-18 Class I | 50 | 100 |
Differential SSTL-18 Class II | 50 | 100 |
Differential SSTL-15 Class I | 50 | 100 |
Differential SSTL-15 Class II | 50 | 100 |
Differential SSTL-15 | 48, 60,120 | 240 |
Differential SSTL-135 | 48, 60, 120 | 240 |
Differential SSTL-125 | 48, 60, 120 | 240 |
Differential SSTL-12 | 60, 120 | 240 |
Differential POD12 | 34, 40, 48, 60, 80, 120, 240 | 240 |
Differential 1.8 V HSTL Class I | 50 | 100 |
Differential 1.8 V HSTL Class II | 50 | 100 |
Differential 1.5 V HSTL Class I | 50 | 100 |
Differential 1.5 V HSTL Class II | 50 | 100 |
Differential 1.2 V HSTL Class I | 50 | 100 |
Differential 1.2 V HSTL Class II | 50 | 100 |
The RT OCT calibration circuit compares the total impedance of the I/O buffer to the external resistor connected to the RZQ pin. The circuit dynamically enables or disables the transistors until the total impedance of the I/O buffer matches the external resistor.
Calibration occurs at the end of the device configuration. When the calibration circuit finds the correct impedance, the circuit powers down and stops changing the characteristics of the drivers.
2.4.4. Dynamic OCT
Dynamic OCT is useful for terminating a high-performance bidirectional path by optimizing the signal integrity depending on the direction of the data. Dynamic OCT also helps save power because device termination is internal. Internal termination switches on only during input operation and thus draws less static power.
Dynamic OCT | Bidirectional I/O | State |
---|---|---|
Dynamic RT OCT | Acts as a receiver | Enabled |
Acts as a driver | Disabled | |
Dynamic RS OCT | Acts as a receiver | Disabled |
Acts as a driver | Enabled |
2.4.5. Differential Input RD OCT
All I/O pins and dedicated clock input pins in Intel® Stratix® 10 devices support on-chip differential termination, RD OCT. The Intel® Stratix® 10 devices provide a 100 Ω, on-chip differential termination option on each differential receiver channel for LVDS standards.
You can enable on-chip termination in the Intel® Quartus® Prime software Assignment Editor.
Field | Assignment |
---|---|
To | rx_in |
Assignment name | Input Termination |
Value | Differential |
2.4.6. OCT Calibration Block in Intel Stratix 10 Devices
You can use RS and RT OCT in the same I/O bank for different I/O standards if the I/O standards use the same VCCIO supply voltage. You cannot configure the RS OCT and the programmable current strength for the same I/O buffer.
The OCT calibration process uses the RZQ pin that is available in every calibration block in a given I/O bank for series- and parallel-calibrated termination:
- Each OCT calibration block has an external 240 Ω reference resistor associated with it through the RZQ pin.
- Connect the RZQ pin to GND through an external 100 Ω or 240 Ω resistor (depending on the RS or RT OCT value).
- The RZQ pin shares the same VCCIO supply voltage with the I/O bank where the pin is located.
- The RZQ pin is a dual-purpose I/O pin and functions as a general purpose I/O pin if you do not use the calibration circuit.
Intel® Stratix® 10 devices support calibrated RS and calibrated RT OCT on all LVDS I/O pins except for dedicated configuration pins.
2.5. External I/O Termination for Intel Stratix 10 Devices
I/O Standard | External Termination Scheme |
---|---|
3.3 V LVTTL/3.3 V LVCMOS | No external termination required |
3.0 V LVTTL/3.0 V LVCMOS | |
2.5 V LVCMOS | |
1.8 V LVCMOS | |
1.5 V LVCMOS | |
1.2 V LVCMOS | |
SSTL-18 Class I and Class II | Single-Ended SSTL I/O Standard Termination |
SSTL-15 Class I and Class II | |
SSTL-15 15 | No external termination required |
SSTL-135 15 | |
SSTL-125 15 | |
SSTL-12 | |
POD12 | Single-Ended POD I/O Standard Termination |
1.8 V HSTL Class I and Class II | Single-Ended HSTL I/O Standard Termination |
1.5 V HSTL Class I and Class II | |
1.2 V HSTL Class I and Class II | |
HSUL-12 | No external termination required |
Differential SSTL-18 Class I and Class II | Differential SSTL I/O Standard Termination |
Differential SSTL-15 Class I and Class II | |
Differential SSTL-15 15 | No external termination required |
Differential SSTL-135 15 | |
Differential SSTL-125 15 | |
Differential SSTL-12 | |
Differential POD12 | Differential POD I/O Standard Termination |
Differential 1.8 V HSTL Class I and Class II | Differential HSTL I/O Standard Termination |
Differential 1.5 V HSTL Class I and Class II | |
Differential 1.2 V HSTL Class I and Class II | |
Differential HSUL-12 | No external termination required |
LVDS | LVDS I/O Standard Termination |
RSDS | RSDS/mini-LVDS I/O Standard Termination |
Mini-LVDS | |
LVPECL | Differential LVPECL I/O Standard Termination |
2.5.1. Single-Ended I/O Termination
Voltage-referenced I/O standards require an input VREF and a termination voltage (VTT). The reference voltage of the receiving device tracks the termination voltage of the transmitting device.
The supported I/O standards such as SSTL-12, SSTL-125, SSTL-135, and SSTL-15 typically do not require external board termination.
Intel recommends that you use OCT with these I/O standards to save board space and cost. OCT reduces the number of external termination resistors used.
2.5.2. Differential I/O Termination for Intel Stratix 10 Devices
The I/O pins are organized in pairs to support differential I/O standards. Each I/O pin pair can support differential input and output buffers.
The supported I/O standards such as Differential SSTL-12, Differential SSTL-15, Differential SSTL-125, and Differential SSTL-135 typically do not require external board termination.
Intel recommends that you use OCT with these I/O standards to save board space and cost. OCT reduces the number of external termination resistors used.
2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination
Differential HSTL, SSTL, HSUL, and POD inputs use LVDS differential input buffers. However, RD support is only available if the I/O standard is LVDS.
Differential HSTL, SSTL, HSUL, and POD outputs are not true differential outputs. These I/O standards use two single-ended outputs with the second output programmed as inverted.
2.5.2.2. LVDS, RSDS, and Mini-LVDS Termination
All I/O banks have dedicated circuitry to support the true LVDS, RSDS, and mini-LVDS I/O standards by using true LVDS output buffers without resistor networks.
2.5.2.3. LVPECL Termination
The Intel® Stratix® 10 devices support the LVPECL I/O standard on input clock pins only:
- LVPECL input operation is supported using LVDS input buffers.
- LVPECL output operation is not supported.
Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the Intel® Stratix® 10 LVPECL input buffer specification.
For information about the VICM specification, refer to the device datasheet.
3. Intel Stratix 10 I/O Design Considerations
3.1. Guideline: VREF Sources and VREF Pins
For Intel® Stratix® 10 devices, consider the following VREF pins guidelines:
-
Intel®
Stratix® 10
devices support internal and external VREF sources.
- There is an external VREF pin for every I/O bank, providing one external VREF source for all I/Os in the same bank.
- Each I/O lane in the bank also has its own internal VREF generator. You can configure each I/O lane independently to use its internal VREF or the I/O bank's external VREF source. All I/O pins in the same I/O lane use the same VREF source.
- You can use the internal VREF with calibration to support DDR4 using the POD12 I/O standard.
- You can place any combination of input, output, or bidirectional pins near VREF pins. There is no VREF pin placement restriction.
- The VREF pins are dedicated for voltage-referenced single-ended I/O standards. You cannot use the VREF pins as user I/Os.
- Connect unused VREF pins to GND.
For more information about pin capacitance of the VREF pins, refer to the device datasheet.
3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing
To ensure device reliability and proper operation when you use the device for 3.0 V I/O interfacing, do not violate the absolute maximum ratings of the device. For more information about absolute maximum rating and maximum allowed overshoot during transitions, refer to the device datasheet.
Single-Ended Transmitter Application
If you use the Intel® Stratix® 10 device as a transmitter, use slow slew rate and series termination to limit the overshoot and undershoot at the I/O pins. Transmission line effects that cause large voltage deviations at the receiver are associated with an impedance mismatch between the driver and the transmission lines. By matching the impedance of the driver to the characteristic impedance of the transmission line, you can significantly reduce overshoot voltage. You can use a series termination resistor placed physically close to the driver to match the total driver impedance to the transmission line impedance.
Single-Ended Receiver Application
If you use the Intel® Stratix® 10 device as a receiver, use an external clamping diode to limit the overshoot and undershoot voltage at the I/O pins.
The 3.0 V I/O standard is supported using the bank supply voltage (VCCIO) at 3.0 V and a VCCPT voltage of 1.8 V. In this method, the clamping diode can sufficiently clamp overshoot voltage to within the DC and AC input voltage specifications. The clamped voltage is expressed as the sum of the VCCIO and the diode forward voltage.
3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards
Non-Voltage-Referenced I/O Standards
An I/O bank can simultaneously support any number of input signals with different I/O standard assignments if the I/O standards support the VCCIO level of the I/O bank.
For output signals, a single I/O bank supports non-voltage-referenced output signals that drive at the same voltage as VCCIO. Because an I/O bank can only have one VCCIO value, it can only drive out the value for non-voltage-referenced signals.
Voltage-Referenced I/O Standards
To accommodate voltage-referenced I/O standards:
- Each Intel® Stratix® 10 FPGA I/O bank contains a dedicated VREF pin.
- Each bank can have only a single VCCIO voltage level and a single voltage reference (VREF) level.
The voltage-referenced input buffer is powered by VCCPT. Therefore, an I/O bank featuring single-ended or differential standards can support different voltage-referenced standards under the following conditions:
- The VREF are the same levels.
- On-chip parallel termination (RT OCT) is disabled.
If you enable RT OCT, the voltage for the input standard and the VCCIO of the bank must match.
This feature allows you to place voltage-referenced input signals in an I/O bank with a VCCIO of 1.8 V or below. For example, you can place HSTL-15 input pins in an I/O bank with 1.8 V VCCIO. However, the voltage-referenced input with RT OCT enabled requires the VCCIO of the I/O bank to match the voltage of the input standard. RT OCT cannot be supported for the HSTL-15 I/O standard when VCCIO is 1.8 V.
Voltage-referenced bidirectional and output signals must be the same as the VCCIO voltage of the I/O bank. For example, you can place only SSTL-18 output pins in an I/O bank with a 1.8 V VCCIO.
Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
An I/O bank can support voltage-referenced and non-voltage-referenced pins by applying each of the rule sets individually.
Examples:
- An I/O bank can support SSTL-18 inputs and outputs, and 1.8 V inputs and outputs with a 1.8 V VCCIO and a 0.9 V VREF.
- An I/O bank can support 1.5 V standards, 1.8 V inputs (but not outputs), and 1.5 V HSTL I/O standards with a 1.5 V VCCIO and 0.75 V VREF.
3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing
The Intel® Stratix® 10 I/O buffers are powered by VCC, VCCPT, and VCCIO.
Because the Intel® Stratix® 10 devices do not support hot socketing, do not drive the I/O pins externally during power up and power down. This includes all I/O pins including FPGA and HPS I/Os. Adhere to this guideline to:
- Avoid excess I/O pin current:
- Excess I/O pin current affects the device's lifetime and reliability.
- Excess current on the 3 V I/O pins can damage the Intel® Stratix® 10 device.
- Achieve minimum current draw and avoid I/O glitch during power up or power down.
- Avoid permanent damage on the 3 V I/O buffers in 3 V operation.
3.5. Guideline: Intel Stratix 10 I/O Buffer During Power Up, Configuration, and Power Down
- During device power up and device configuration, all GPIO pins are tri-stated with weak pull-up enabled.
- During device power down, all I/O pins are in undetermined state and the pin signal is measured between GND and the VCCIO level.
- At any point,the input signal sof an I/O pin must not exceed the maximum DC input voltage specified in the device datasheet.
3.6. Guideline: Maximum DC Current Restrictions
Intel® Stratix® 10 devices conform to the VCCIO Electro-Migration (EM) rule and IR drop targets for all I/O standard drive strength settings—ensuring reliability over the lifetime of the devices.
3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks
3.8. Guideline: I/O Standards Limitation for Intel Stratix 10 TX 400
On the Intel® Stratix® 10 TX 400 device, do not use the following I/O standards in I/O banks 3A and 3D except in dedicated clock pins:
- LVDS
- Mini-LVDS
- RSDS
3.9. Guideline: I/O Standards Limitation for Intel Stratix 10 GX 400 and SX 400
- On the
Intel®
Stratix® 10
GX 400 or SX 400 device, do not use the following I/O standards in I/O banks 3A and
3D except in dedicated clock pins:
- LVDS
- Mini-LVDS
- RSDS
- Bank 3D has only 30 GPIO pins and supports only 1.8 V I/O standards.
- Bank 3C supports only unidirectional single-ended I/O in 3.3 V or 3.0 V I/O standard.
- In bank 3C, the control of I/O direction and features such as current
strength is per eight-pin groups basis.
- To identify the pin groups, refer to the Optional Function(s) column in device pin out files. For example, the group name is IO33_LS[<group index>]_[<pin index>].
- As an example, if you configure any I/O pins from group LS1 as input, all the other pins in the group use the same setting. Similarly, if you use a pin in group LS0 as an output pin with 12 mA current strength, all pins in group LS0 apply the same setting.
- You cannot configure input and output pins in the same group. You can only use all eight pins as input, or all eight pins as output.
- If you use 3 V I/O standard in the design without assigning pin locations, the Intel® Quartus® Prime software automatically assigns the pins to bank 3C. If you want to assign the 3 V I/O standard to the 3 V I/O bank, specify the USE_AS_3V_GPIO Intel® Quartus® Prime assignment to the pin in the .qsf file.
Pin Group | Entry in Optional Function(s) Column | Pin Name |
---|---|---|
LS1 | IO33_LS1_0 | Y2 |
IO33_LS1_1 | AA2 | |
IO33_LS1_2 | AB1 | |
IO33_LS1_3 | AB2 | |
IO33_LS1_4 | AC1 | |
IO33_LS1_5 | AD1 | |
IO33_LS1_6 | AF2 | |
IO33_LS1_7 | AG2 | |
LS0 | IO33_LS0_0 | U3 |
IO33_LS0_1 | V3 | |
IO33_LS0_2 | U5 | |
IO33_LS0_3 | V4 | |
IO33_LS0_4 | W2 | |
IO33_LS0_5 | Y1 | |
IO33_LS0_6 | W3 | |
IO33_LS0_7 | W4 |
4. Intel Stratix 10 I/O Implementation Guides
The Intel® Quartus® Prime software allows you to prepare for device migration, set pin assignments, define placement restrictions, setup timing constraints, and customize IP cores. For more information about using the Intel® Quartus® Prime software, refer to the related information.
4.1. GPIO Intel FPGA IP
The GPIO IP core supports the GPIO components and features of the Intel® Stratix® 10 device family. You can use the Intel® Quartus® Prime parameter editor to configure the GPIO IP core.
Components of the GPIO IP core:
- Double data rate input/output (DDIO)—doubles or halves the data-rate of a communication channel
- Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure
- I/O buffers—connect the pads to the FPGA
4.1.1. Release Information for GPIO Intel FPGA IP
Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 19.3.0 |
Intel® Quartus® Prime Version | 20.3 |
Release Date | 2020.09.28 |
4.1.2. GPIO Intel FPGA IP Data Paths
Data Path | Register Mode | |||
---|---|---|---|---|
Bypass | Simple Register | DDR I/O | ||
Full-Rate | Half-Rate | |||
Input | Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). | The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. | The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data. |
Output | Data goes from the core straight to the delay element, bypassing all DDIOs. | The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. | The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data. |
Bidirectional | The output buffer drives both an output pin and an input buffer. | The full-rate DDIO operates as a simple register. The output buffer drives both an output pin and an input buffer. | The full-rate DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. |
If you use asynchronous clear and preset signals, all DDIOs share these same signals.
Half-rate and full-rate DDIOs connect to separate clocks. When you use half-rate and full-rate DDIOs, the full-rate clock must run at twice the half-rate frequency. You can use different phase relationships to meet timing requirements.
4.1.2.1. Input Path
The 3 V I/Os do not support DDIOs.
- The pad receives data.
- DDIO IN (1) captures data on the rising and falling edges of ck_fr and sends the data, signals (A) and (B) in the following waveform figure, at single data rate.
- DDIO IN (2) and DDIO IN (3) halve the data rate.
- dout[3:0] presents the data as a half-rate bus.
In this figure, the data goes from full-rate clock at double data rate to half-rate clock at single data rate. The data rate is divided by four and the bus size is increased by the same ratio. The overall throughput through the GPIO IP core remains unchanged.
The actual timing relationship between different signals may vary depending on the specific design, delays, and phases that you choose for the full-rate and half-rate clocks.
4.1.2.2. Output and Output Enable Paths
Each LVDS I/O output path contains two stages of DDIOs, which are half-rate and full-rate.
The 3 V I/Os do not support DDIOs.
The difference between the output path and output enable (OE) path is that the OE path does not contain full-rate DDIO. To support packed-register implementations in the OE path, a simple register operates as full-rate DDIO. For the same reason, only one half-rate DDIO is present.
The OE path operates in the following three fundamental modes:
- Bypass—the core sends data directly to the delay element, bypassing all DDIOs.
- Packed Register—bypasses half-rate DDIO.
- SDR output at half-rate—half-rate DDIOs convert data from full-rate to half-rate.
In Intel® Stratix® 10 devices, each 3 V I/O bank supports only two output enables (OE) for its eight single-ended I/Os.
4.1.3. Register Packing
The GPIO IP core allows you to pack register into the periphery to save area and resource utilization.
You can configure the full-rate DDIO on the input and output path as a flip flop. To do so, add the .qsf assignments listed in this table.
Path | QSF Assignment |
---|---|
Input register packing | set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register> |
Output register packing | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register> |
Output enable register packing | set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to register> |
4.2. Verifying Resource Utilization and Design Performance
- On the menu, click Processing > Start Compilation to run a full compilation.
- After compiling the design, click Processing > Compilation Report.
-
Using the Table of Contents,
navigate to Fitter > Resource Section.
- To view the resource usage information, select Resource Usage Summary.
- To view the resource utilization information, select Resource Utilization by Entity.
4.3. GPIO Intel FPGA IP Timing
4.3.1. Timing Components
- I/O interface paths—from the FPGA to external receiving devices and from external transmitting devices to the FPGA.
- Core interface paths of data and clock—from the I/O to the core and from the core to I/O.
- Transfer paths—from half-rate to full-rate DDIO, and from full-rate to half-rate DDIO.
4.3.2. Delay Elements
Delay Element | .qsf Assignment |
---|---|
Input Delay Element | set_instance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63> |
Output Delay Element | set_instance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15> |
Output Enable Delay Element | set_instance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15> |
4.3.3. Timing Analysis
Follow the timing guidelines and examples to ensure that the Timing Analyzer analyzes the I/O timing correctly.
- To perform proper timing analysis for the I/O interface paths, specify the system level constraints of the data pins against the system clock pin in the .sdc file.
- To perform proper timing analysis for the core interface paths, define these clock
settings in the .sdc file:
- Clock to the core registers
- Clock to the I/O registers for the simple register and DDIO modes
4.3.3.1. Single Data Rate Input Register
Command | Command Example | Description |
---|---|---|
create_clock | create_clock -name sdr_in_clk -period "100 MHz" sdr_in_clk | Creates clock setting for the input clock. |
set_input_delay | set_input_delay -clock sdr_in_clk 0.15 sdr_in_data | Instructs the Timing Analyzer to analyze the timing of the input I/O with a 0.15 ns input delay. |
4.3.3.2. Full-Rate or Half-Rate DDIO Input Register
Command | Command Example | Description |
---|---|---|
create_clock |
create_clock -name virtual_clock -period "200 MHz" create_clock -name ddio_in_clk -period "200 MHz" ddio_in_clk |
Create clock setting for the virtual clock and the DDIO clock. |
set_input_delay |
set_input_delay -clock virtual_clock 0.25 ddio_in_data set_input_delay -add_delay -clock_fall -clock virtual_clock 0.25 ddio_in_data |
Instruct the Timing Analyzer to analyze the positive clock edge and the negative clock edge of the transfer. Note the -add_delay in the second set_input_delay command. |
set_false_path |
set_false_path -fall_from virtual_clock -rise_to ddio_in_clk set_false_path -rise_from virtual_clock -fall_to ddio_in_clk |
Instruct the Timing Analyzer to ignore the positive clock edge to the negative edge triggered register, and the negative clock edge to the positive edge triggered register. Note: The ck_hr frequency must be half the ck_fr frequency. If the I/O PLL drives the clocks, you can consider using the derive_pll_clocks
.sdc command.
|
4.3.3.3. Single Data Rate Output Register
Command | Command Example | Description |
---|---|---|
create_clock and create_generated_clock |
create_clock -name sdr_out_clk -period "100 MHz" sdr_out_clk create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk |
Generate the source clock and the output clock to transmit. |
set_output_delay | set_output_delay -clock sdr_out_clk 0.45 sdr_out_data | Instructs the Timing Analyzer to analyze the output data to transmit against the output clock to transmit. |
4.3.3.4. Full-Rate or Half-Rate DDIO Output Register
Command | Command Example | Description |
---|---|---|
create_clock and create_generated_clock |
create_clock -name ddio_out_fr_clk -period "200 MHz" ddio_out_fr_clk create_generated_clock -source ddio_out_fr_clk -name ddio_out_fr_outclk ddio_out_fr_outclk |
Generate the clocks to the DDIO and the clock to transmit. |
set_output_delay |
set_output_delay -clock ddio_out_fr_outclk 0.55 ddio_out_fr_data set_output_delay -add_delay -clock_fall -clock ddio_out_fr_outclk 0.55 ddio_out_fr_data |
Instruct the Timing Analyzer to analyze the positive and negative data against the output clock. |
set_false_path |
set_false_path -rise_from ddio_out_fr_clk -fall_to ddio_out_fr_outclk set_false_path -fall_from ddio_out_fr_clk -rise_to ddio_out_fr_outclk |
Instruct the Timing Analyzer to ignore the rising edge of the source clock against the falling edge of the output clock, and the falling edge of source clock against rising edge of output clock |
4.3.4. Timing Closure Guidelines
To meet the hold time, add delay to the input data path using the input delay chain. In general, the input delay chain is around 30 ps per step at the –1 speed grade. To get an approximate input delay chain setting to pass the timing, divide the negative hold slack by 60 ps.
However, if the I/O PLL drives the clocks of the GPIO input registers (simple register or DDIO mode), you can set the compensation mode to source synchronous mode. The Fitter will attempt to configure the I/O PLL for a better setup and hold slack for the input I/O timing analysis.
For the GPIO output and output enable registers, you can add delay to the output data and clock using the output and output enable delay chains.
- If you observe setup time violation, you can increase the output clock delay chain setting.
- If you observe hold time violation, you can increase the output data delay chain setting.
4.4. GPIO Intel FPGA IP Design Examples
You can generate the design examples from the GPIO IP core parameter editor. After you setting the parameters that you want, click Generate Example Design. The IP core generates the design example source files in the directory you specify.
4.4.1. GPIO IP Core Synthesizable Intel Quartus Prime Design Example
Generating and Using the Design Example
To generate the synthesizable Intel® Quartus® Prime design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following command:
quartus_sh -t make_qii_design.tcl [device_name]
The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.
4.4.2. GPIO IP Core Simulation Design Example
Using the design example, you can run a simulation using a single command, depending on the simulator that you use. The simulation demonstrates how you can use the GPIO IP core.
Generating and Using the Design Example
To generate the simulation design example from the source files for a Verilog simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl
To generate the simulation design example from the source files for a VHDL simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VHDL
The TCL script creates a sim directory that contains subdirectories—one for each supported simulation tool. You can find the scripts for each simulation tool in the corresponding directories.
4.5. Verifying Pin Migration Compatibility
You can use the Pin Migration View window in the Intel® Quartus® Prime software Pin Planner to assist you in verifying whether your pin assignments migrate to a different device successfully. You can vertically migrate to a device with a different density while using the same device package, or migrate between packages with different densities and ball counts.
- Open Assignments > Pin Planner and create pin assignments.
-
If necessary,
perform one of the following options to populate the Pin Planner with the node
names in the design:
- Analysis & Elaboration
- Analysis & Synthesis
- Fully compile the design
- Then, on the menu, click View > Pin Migration View.
-
To select or change
migration devices:
- Click Device to open the Device dialog box.
- Under Migration compatibility click Migration Devices.
-
To show more
information about the pins:
- Right-click anywhere in the Pin Migration View window and select Show Columns.
- Then, click the pin feature you want to display.
- If you want to view only the pins, in at least one migration device, that have a different feature than the corresponding pin in the migration result, turn on Show migration differences.
-
Click Pin Finder to open the Pin Finder dialog box to find and highlight pins
with specific functionality.
If you want to view only the pins highlighted by the most recent query in the Pin Finder dialog box, turn on Show only highlighted pins.
- To export the pin migration information to a Comma-Separated Value file (.csv), click Export.
4.6. IP Migration to the GPIO IP Core
Depending on the mode you use in your previous IP, the IP migration tool can automatically configure the new GPIO IP core based on settings in your previous IP. For unsupported modes, you can use the GPIO IP core parameter editor to manually configure the migrated IP core.
4.6.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores
To migrate your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP cores to the GPIO Intel® FPGA IP IP core, follow these steps:
- Open your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF IP core in the IP Parameter Editor.
- In the Currently selected device family, select Stratix 10.
-
Click Finish to open the GPIO IP Parameter Editor.
The IP Parameter Editor configures the GPIO IP core settings similar to the ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF core settings.
- If there are any incompatible settings between the two, select new supported settings.
- Click Finish to regenerate the IP core.
- Replace your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF IP core instantiation in RTL with the GPIO IP core.
4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
The GPIO IP core drives these ports to the output registers on these clock edges:
- datain_h—on the falling edge of outclock
- datain_l—on the rising edge of outclock
If you migrated your GPIO IP from Stratix® V, Arria® V, and Cyclone® V devices, swap the datain_h and datain_l ports when you instantiate the IP generated by the GPIO IP core.
5. GPIO Intel FPGA IP Reference
The Intel® Quartus® Prime software generates your customized GPIO IP core according to the parameter options that you set in the IP parameter editor.
5.1. GPIO Intel FPGA IP Parameter Settings
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Data Direction | — |
|
Specifies the data direction for the GPIO. |
Data width | — |
1 to 128 |
Specifies the data width. |
Use legacy top-level port names | — |
|
Use same port names as in Stratix® V, Arria® V, and Cyclone® V devices. For example, dout becomes dataout_h and dataout_l, and din becomes datain_h and datain_l. Note: The behavior of these ports are different than in the
Stratix® V,
Arria® V, and
Cyclone® V
devices. For the migration guideline, refer to the related
information.
|
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Use differential buffer | — |
|
If turned on, enables differential I/O buffers. |
Use pseudo differential buffer |
|
|
If turned on in output mode, enables pseudo differential output buffers. This option is automatically turned on for bidirectional mode if you turn on Use differential buffer. |
Use bus-hold circuitry |
|
|
If turned on, the bus hold circuitry can weakly hold the signal on an I/O pin at its last-driven state where the output buffer state will be 1 or 0 but not high-impedance. |
Use open drain output |
|
|
If turned on, the open drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system. |
Enable output enable port | Data Direction = Output |
|
If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode. In Intel® Stratix® 10 devices, each 3 V I/O bank supports only two output enables (OE) for its eight single-ended I/Os. |
Enable seriestermination / paralleltermination ports | — |
|
If turned on, enables the seriesterminationcontrol and parallelterminationcontrol ports of the output buffer. |
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Register mode | — |
|
Specifies the register mode for the
GPIO IP core:
If you use an I/O standard supported only by the 3 V I/O banks, select None. |
Enable synchronous clear / preset port |
|
|
Specifies how to implement synchronous reset port.
|
Enable asynchronous clear / preset port |
|
|
Specifies how to implement asynchronous reset port.
ACLR and ASET signals are active high. |
Enable clock enable ports | Register mode = DDIO |
|
|
Half Rate logic | Register mode = DDIO |
|
If turned on, enables half-rate DDIO. |
Separate input / output Clocks |
|
|
If turned on, enables separate clocks (CK_IN and CK_OUT) for the input and output paths in bidirectional mode. |
5.2. GPIO Intel FPGA IP Interface Signals
Signal Name | Direction | Description |
---|---|---|
pad_in[SIZE-1:0] | Input |
Input signal from the pad. |
pad_in_b[SIZE-1:0] | Input |
Negative node of the differential input signal from the pad. This port is available if you turn on the Use differential buffer option. |
pad_out[SIZE-1:0] | Output | Output signal to the pad. |
pad_out_b[SIZE-1:0] | Output |
Negative node of the differential output signal to the pad. This port is available if you turn on the Use differential buffer option. |
pad_io[SIZE-1:0] | Bidirectional |
Bidirectional signal connection with the pad. |
pad_io_b[SIZE-1:0] | Bidirectional |
Negative node of the differential bidirectional signal connection with the pad. This port is available if you turn on the Use differential buffer option. |
Signal Name | Direction | Description |
---|---|---|
din[DATA_SIZE-1:0] | Input |
Data input from the FPGA core in output or bidirectional mode. DATA_SIZE depends on the register mode:
|
dout[DATA_SIZE-1:0] | Output |
Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode:
|
oe[OE_SIZE-1:0] | Input |
OE input from the FPGA core in output mode with Enable output enable port turned on, or bidirectional mode. OE is active high. When transmitting data, set this signal to 1. When receiving data, set this signal to 0. OE_SIZE depends on the register mode:
|
Signal Name | Direction | Description |
---|---|---|
ck | Input |
In input and output paths, this clock feeds a packed register or DDIO if you turn off the Half Rate logic parameter. In bidirectional mode, this clock is the unique clock for the input and output paths if you turn off the Separate input/output Clocks parameter. |
ck_fr | Input |
In input and output paths, these clocks feed the full-rate and half-rate DDIOs if your turn on the Half Rate logic parameter. In bidirectional mode, the input and output paths use these clocks if you turn off the Separate input/output Clocks parameter. |
ck_hr | ||
ck_in | Input |
In bidirectional mode, these clocks feed a packed register or DDIO in the input and output paths if you specify both these settings:
|
ck_out | ||
ck_fr_in | Input |
In bidirectional mode, these clocks feed a full-rate and half-rate DDIOS in the input and output paths if you specify both these settings
For example, ck_fr_out feeds the full-rate DDIO in the output path. |
ck_fr_out | ||
ck_hr_in | ||
ck_hr_out | ||
cke | Input | Clock enable. |
Signal Name | Direction | Description |
---|---|---|
seriesterminationcontrol | Input | Input from the termination control block (OCT) to the buffers. It sets the buffer series impedance value. |
parallelterminationcontrol | Input | Input from the termination control block (OCT) to the buffers. It sets the buffer parallel impedance value. |
Signal Name | Direction | Description |
---|---|---|
sclr | Input | Synchronous clear input. Not available if you enable sset. |
aclr | Input | Asynchronous clear input. Active high. Not available if you enable aset. |
aset | Input | Asynchronous set input. Active high. Not available if you enable aclr. |
sset | Input | Synchronous set input. Not available if you enable sclr. |
5.2.1. Shared Signals
- The input, output, and OE paths share the same clear and preset signals.
- The output and OE path shares the same clock signals.
5.2.2. Data Bit-Order for Data Interface
- If the data bus size value is SIZE, the LSB is at the right-most position.
- If the data bus size value is 2 × SIZE, the bus is made of two words of SIZE .
- If the data bus size value 4 × SIZE, the bus is made of four words of SIZE.
- The LSB is in the right-most position of each word.
- The right-most word specifies the first word going out for output buses and the first word coming in for input buses.
5.2.3. Data Interface Signals and Corresponding Clocks
Signal Name | Parameter Configuration | Clock | ||
---|---|---|---|---|
Register Mode | Half Rate | Separate Clocks | ||
din |
|
Off | Off | ck |
DDIO | On | Off | ck_hr | |
|
Off | On | ck_in | |
DDIO | On | On | ck_hr_in | |
|
|
Off | Off | ck |
DDIO | On | Off | ck_hr | |
|
Off | On | ck_out | |
DDIO | On | On | ck_hr_out | |
|
|
Off | Off | ck |
DDIO | On | Off | ck_fr | |
|
Off | On |
|
|
DDIO | On | On |
|
6. Intel Stratix 10 General Purpose I/O User Guide Archives
Intel® Quartus® Prime Version | User Guide |
---|---|
20.2 | Intel® Stratix® 10 General Purpose I/O User Guide |
19.4 | Intel® Stratix® 10 General Purpose I/O User Guide |
19.3 | Intel® Stratix® 10 General Purpose I/O User Guide |
19.2 | Intel® Stratix® 10 General Purpose I/O User Guide |
18.1 | Intel® Stratix® 10 General Purpose I/O User Guide |
18.0 | Intel® Stratix® 10 General Purpose I/O User Guide |
17.1 | Intel® Stratix® 10 General Purpose I/O User Guide |
7. Document Revision History for Intel Stratix 10 General Purpose I/O User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2020.11.13 | 20.3 | Updated the figure showing the I/O bank structure to add the pin naming orientation. |
2020.08.25 | 20.2 | Updated the topic about the I/O and differential I/O buffers to remove differential I/O support from 3 V I/O bank and to improve clarity. |
2020.07.14 | 20.2 |
|
2020.01.08 | 19.4 |
|
2019.10.01 | 19.3 |
Corrected typographical error in the .qsf assignment codes in the topic about delay elements. |
2019.09.30 | 19.3 |
|
2019.07.09 | 19.2 |
Updated the notes in the topics about the input path, and output and output enable paths to specify that the GPIO Intel® FPGA IP and OCT Intel® FPGA IP support OCT on single-directional input or output pins only. |
2019.03.04 | 18.1 | In the topics about the input path,
and output and output enable paths:
|
2019.01.23 | 18.1 |
Updated the Intel® Quartus® Prime version of the document. |
2019.01.14 | 18.1 |
|
2018.07.09 | 18.0 |
|
2018.05.10 | 18.0 |
|
Date | Version | Changes |
---|---|---|
November 2017 | 2017.11.06 |
|
September 2017 | 2017.09.04 |
|
February 2017 | 2017.02.13 |
|
December 2016 | 2016.12.05 | Corrected the number of I/Os in I/O bank 3L for the HF55 package of the GX 4500 and SX 5500 devices. |
October 2016 | 2016.10.31 |
Initial release. |