L- and H-Tile Transceiver PHY User Guide
1. Overview
Intel® Stratix® 10 devices offer up to 144 transceivers with integrated advanced high-speed analog signal conditioning and clock data recovery circuits for chip-to-chip, chip-to-module, and backplane applications.
The Intel® Stratix® 10 devices contain a combination of GX, GXT, or GXE channels, in addition to the hardened IP blocks for PCI Express* and Ethernet applications.
The Intel® Stratix® 10 device introduces several transceiver tile variants to support a wide variety of protocol implementations. These transceiver tile variants are L-tiles, H-tiles, and E-tiles. This user guide describes both the L- and H-tile transceivers. For Intel® Stratix® 10 devices that only contain E-tiles, refer to the E-Tile Transceiver PHY User Guide.
Feature | L-Tile | H-Tile | E-Tile |
---|---|---|---|
Maximum Transceiver Data Rate (Chip-to-chip) |
GX 1—17.4 Gbps GXT 1—26.6 Gbps |
GX—17.4 Gbps GXT—28.3 Gbps |
GXE 2—57.8 Gbps Pulse Amplitude Modulation 4 (PAM4)/28.9 Gbps Non-return to zero (NRZ) |
Maximum Transceiver Data Rate (Backplane) |
GX—12.5 Gbps GXT—12.5 Gbps |
||
Number of Transceiver Channels (per tile) |
GX—16 per tile GXT—8 per tile Total—24 per tile (4 banks, 6 channels per bank) |
GX—8 per tile GXT—16 per tile Total—24 per tile (4 banks, 6 channels per bank) |
GXE—24 individual channels per tile |
Hard IP (per tile) | PCIe* —Gen3 x16 |
PCIe* —Gen3 x16, SR-IOV (4 PF, 2K VF) Ethernet—100GbE MAC |
Ethernet—100GbE MAC and RS (528, 514)-FEC, 4 per tile Ethernet—KP-FEC, 4 per tile Ethernet—10/25GbE MAC and RS (528, 514)-FEC, 24 per tile |
In all Intel® Stratix® 10 devices, the various transceiver tiles connect to the FPGA fabric using Intel EMIB (Embedded Multi-Die Interconnect Bridge) technology.
1.1. L-Tile/H-Tile Layout in Intel Stratix 10 Device Variants
Intel® Stratix® 10 GX/SX device variants support both L- and H-Tiles. Intel® Stratix® 10 TX and MX device variants support both H- and E-Tiles.
Intel® Stratix® 10 devices are offered in a number of different configurations based on layout. There is a maximum of six possible locations for a tile. The following figure maps these layouts to the corresponding transceiver tiles and banks.
1.1.1. Intel Stratix 10 GX/SX H-Tile Configurations
The Intel® Stratix® 10 GX FPGAs meet the high-performance demands of high-throughput systems with up to 10 teraflops (TFLOPs) of floating-point performance. Intel® Stratix® 10 GX FPGAs also provide transceiver support up to 28.3 Gbps for chip-module, chip-to-chip, and backplane applications.
The Intel® Stratix® 10 SX SoCs features a hard processor system with 64 bit quad-core ARM* Cortex*-A53 processor available in all densities, in addition to all the features of Intel® Stratix® 10 GX devices.
1.1.2. Intel Stratix 10 TX H-Tile and E-Tile Configurations
The Intel® Stratix® 10 TX FPGAs deliver the most advanced transceiver capabilities in the industry by combining H-Tile and E-Tile transceivers.
- No package migration available between GX/SX and TX device families (H-Tile and E-Tile)
- Migration available within GX/SX from L-Tile to H-Tile variants
1.1.3. Intel Stratix 10 MX H-Tile and E-Tile Configurations
The Intel® Stratix® 10 MX devices combine the programmability and flexibility of Intel® Stratix® 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The DRAM memory tile physically connects to the FPGA using Intel Embedded Multi-Die Interconnect Bridge (EMIB) technology.
1.2. L-Tile/H-Tile Counts in Intel Stratix 10 Devices and Package Variants
Intel® Stratix® 10 GX/SX Device Name |
F1152 HF35 (35x35 mm2) |
F1760A NF43 (42.5x42.5 mm2) |
F2397B UF50 (50x50 mm2) |
F2912E HF55 (55x55 mm2) |
F4938 NF74 (70x74 mm2) |
---|---|---|---|---|---|
GX 400/ SX 400 |
1 | ||||
GX 650/ SX 650 |
1 | ||||
GX 850/ SX 850 |
2 | ||||
GX 1100/ SX 1100 |
2 | ||||
GX 1650/ SX 1650 |
2 | 4 | |||
GX 2100/ SX 2100 |
2 | 4 | |||
GX 2500/ SX 2500 |
2 | 4 | 1 | ||
GX 2800/ SX 2800 |
2 | 4 | 1 | ||
GX 1660 | 2 | ||||
GX 2110 | 2 | ||||
GX 10200 | 4 |
Intel® Stratix® 10 TX Device Name |
F1152 HF35 (35x42.5 mm2) |
F1760C NF43 (42.5x42.5 mm2) |
F2397C SF50, UF50 (50x50 mm2) |
F2912B YF55 (55x55 mm2) |
---|---|---|---|---|
TX 850 | — | 1, 1 | 1, 2 | — |
TX 1100 | — | 1, 1 | 1, 2 | — |
TX 1650 | — | — | 1, 3 | — |
TX 2100 | — | — | 1, 3 | — |
TX 2500 | — | — | 1, 3 | 1, 5 |
TX 2800 | — | — | 1, 3 | 1, 5 |
Intel® Stratix® 10 MX Device Name |
F2597A UF53 (52.5x52.5 mm2) |
F2597B NF53 (52.5x52.5 mm2) |
F2597C UF53 (52.5x52.5 mm2) |
F2912 UF55 (55x55 mm2) |
---|---|---|---|---|
MX 1650 | 4, 0 | — | 4, 0 | 1, 3 |
MX 2100 | 4, 0 | 2, 0 | 4, 0 | 1, 3 |
1.3. L-Tile/H-Tile Building Blocks
1.3.1. Transceiver Bank Architecture
Each L-Tile/H-tile transceiver tile contains four transceiver banks. The transceiver channels are grouped into transceiver banks, where each bank has six channels. These six channels are a combination of GX and GXT channels which you can configure in the following ways:
- All six channels as GX channels
- Channels 0, 1, 3, and 4 as GXT channels. L-Tile supports GXT channels in banks 1 and 3. H-Tile supports GXT channels in banks 0, 1, 2, and 3.
- All six channels as a mix of GX and GXT channels; for example, two GX channels and four GXT channels on H-Tile Devices. On L-Tile devices, you can use a maximum of four channels in a bank when any channel is configured as a GXT channel.
Each channel can also run in any of the following operational modes:
- Duplex (default)—Specifies a single channel that supports both transmission and reception
- Transmitter (TX) Simplex—Specifies a single channel that supports only transmission
- Receiver (RX) Simplex—Specifies a single channel that supports only reception
Each transceiver bank contains two Advanced Transmit (ATX) PLLs, two fractional PLLs (fPLL), and two Clock Multiplier Unit (CMU) PLLs.
1.3.2. Transceiver Channel Types
1.3.2.1. GX Channel
Each GX transceiver channel has four types of PCS blocks that together support continuous datarates up to 17.4 Gbps. The various PCS blocks contain data processing functions such as encoding or decoding, scrambling or descrambling, word alignment, frame synchronization, FEC, and so on.
PCS Type | L-Tile Production | H-Tile Production | |||
---|---|---|---|---|---|
-2 Speed Grade | -3 Speed Grade | -1 Speed Grade | -2 Speed Grades | -3 Speed Grade | |
Standard PCS | 12 Gbps 3 or 10.81344 Gbps 4 | 9.8304 Gbps4 | 12 Gbps3 or 10.81344 Gbps4 | 12 Gbps3 or 10.81344 Gbps4 | 9.8304 Gbps4 |
Enhanced PCS | 17.4 Gbps | ||||
PCIe Gen3 PCS | 8 Gbps | ||||
PCS Direct | 17.4 Gbps |
Refer to Table 12 for a definition of the PCS Direct mode.
1.3.2.2. GXT Channel
Each GXT transceiver channel has two types of PCS blocks that together support continuous datarates up to 28.3 Gbps for H-Tile and 26.6 Gbps for L-Tile. Use PCS Direct or Enhanced PCS to implement a GXT channel.
Refer to the Intel® Stratix® 10 Device Datasheet for more details on transceiver specifications.
PCS Type | L-Tile Production | H-Tile Production | |||
---|---|---|---|---|---|
-2 Speed Grade | -3 Speed Grade | -1 Speed Grade | -2 Speed Grades | -3 Speed Grade | |
Enhanced PCS | 26.6 Gbps | No GXT | 28.3 Gbps | 26.6 Gbps | No GXT |
PCS Direct | 26.6 Gbps | No GXT | 28.3 Gbps | 26.6 Gbps | No GXT |
1.3.3. GX and GXT Channel Placement Guidelines
Refer to AN 778: Intel® Stratix® 10 Transceiver Usage for detailed information on this section.
1.3.4. GXT Channel Usage
Intel® Stratix® 10 L-Tile/H-Tile transceivers support GXT channels.
Tile | Channel Type | Number of Channels per Tile | Channel Capability | |
---|---|---|---|---|
Chip-to-Chip | Backplane | |||
L-Tile | GX | Up to 24 | 17.4 Gbps | 12.5 Gbps |
GXT 5 | Up to 8 | 26.6 Gbps | 12.5 Gbps | |
H-Tile | GX | Up to 24 | 17.4 Gbps | |
GXT 5 | Up to 16 | 28.3 Gbps | 28.3 Gbps |
An ATX PLL can serve as the transmit PLL for up to six GXT channels.
Refer to AN 778: Intel® Stratix® 10 Transceiver Usage for detailed information about this section.
1.3.5. PLL and Clock Networks
There are two different types of clock networks to distribute the high speed serial clock to the channels:
- Transceiver clock network that supports GX channels and allows a single TX PLL to drive up to 24 bonded channels in a tile.
- High Performance clock network that allows a single ATX PLL to drive up to 6 GXT channels in unbonded configurations.
Clock Network | Clock Lines | Channel Type Support |
---|---|---|
Standard | x1, x6, x24 | GX |
High Performance | PLL Direct Connect | GXT |
1.3.5.1. PLLs
1.3.5.1.1. Transceiver Phase-Locked Loops
Each transceiver channel in Intel® Stratix® 10 devices has direct access to three types of high performance PLLs:
- Advanced Transmit (ATX) PLL
- Fractional PLL (fPLL)
- Channel PLL / Clock Multiplier Unit (CMU) PLL.
These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.
Advanced Transmit (ATX) PLL
Fractional PLL (fPLL)
A fractional PLL (fPLL) is an alternate transmit PLL used for generating lower clock frequencies for lower datarate applications. fPLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX PLL, you can also use the fPLL to synthesize frequencies that can drive the core through the FPGA fabric clock networks.
Channel PLL (CMU/CDR PLL)
A channel PLL is located within each transceiver channel. The channel's primary function is clock and data recovery in the transceiver channel when you use the PLL in clock data recovery (CDR) mode. You can use the channel PLLs of channel 1 and 4 as transmit PLLs when configured in clock multiplier unit (CMU) mode. You cannot configure the channel PLLs of channel 0, 2, 3, and 5 in CMU mode; therefore, you cannot use them as transmit PLLs. You cannot use the receiver channel when you use it as a Channel PLL/CMU.
1.3.5.1.2. Clock Generation Block (CGB)
Intel® Stratix® 10 devices include the following types of clock generation blocks (CGBs):
- Master CGB
- Local CGB
Transceiver banks have two master CGBs. The master CGB divides and distributes bonded clocks to a bonded channel group. The master CGB also distributes non-bonded clocks to non-bonded channels across the x6/x24 clock network.
Each transceiver channel has a local CGB. The local CGB divides and distributes non-bonded clocks to the corresponding PCS and PMA blocks.
1.3.5.2. Input Reference Clock Sources
- Eight dedicated reference clocks available per transceiver tile
- Two reference clocks per transceiver bank
- You must route multiple copies of reference clocks on the PCB to span beyond a transceiver tile
- Reference clock network
- Reference clock network does not span beyond the transceiver tile
- There are two regulated reference clock networks for better performance per tile that any reference clock pin can access
- You can use unused receiver pins as additional reference clocks
For the best jitter performance, place the reference clock as close as possible to the transmit PLL. Use the reference clock in the same triplet of the bank as the transmit PLL.
1.3.5.3. Transceiver Clock Network
1.3.5.3.1. x1 Clock Lines
For more information, refer to the x1 Clock Lines section.
1.3.5.3.2. x6 Clock Lines
For more information, refer to the x6 Clock Lines section.
1.3.5.3.3. x24 Clock Lines
Route the x6 clock lines onto x24 clock lines to allow a single ATX PLL or fPLL to drive multiple bonded or non-bonded transmit channels in multiple banks in an L-/H-Tile.
1.3.5.3.4. GXT Clock Network
The GXT Clock Network allows the ATX PLL to drive up to six GXT channels in non-bonded mode.
The top ATX PLL in a bank can drive:
- Channels 0, 1, 3, 4 in the bank
- Channels 0, 1 in the bank above in the same H-Tile
The bottom ATX PLL in a bank can drive:
- Channels 0, 1, 3, 4 in the bank
- Channels 3, 4 in the bank below in the same H-Tile
1.3.6. Ethernet Hard IP
1.3.6.1. 100G Ethernet MAC Hard IP
- Supported Protocols
- 100G MAC + PCS Ethernet x4 lanes
- Modes
- MAC + PCS
- PCS only
- PCS66 (encoder/scrambler bypass)
- Loopbacks
- AN/LT with soft logic: dynamic switching
- Requires a soft Auto Negotiation / Link Training (AN/LT) logic implemented in the core fabric. Implement the AN/LT logic, or use a MAC IP.
Auto negotiation (AN) is an exchange in which link partners to determine the highest performance datarate that they both support. Link training (LT) is the process that defines how a receiver (RX) and a transmitter (TX) on a high-speed serial link communicate with each other to tune their PMA settings.
The protocol specifies how to request the link partner TX driver to adjust TX deemphasis, but the standard does not state how or when to adjust receiver equalization. The manufacturer determines how they adjust their receiver equalization. The algorithm for RX settings is different between tiles.
1.3.6.2. 100G Configuration
The Ethernet Hard IP uses 5 channels in the top transceiver bank of the tile. Channels 0, 1, 3 and 4 send or receive data at 25 Gbps. Channel 2 bonds the 4 transceiver channels and it cannot be used for other purposes.
1.3.7. PCIe Gen1/Gen2/Gen3 Hard IP Block
The PCIe Hard IP is an IP block that provides multiple layers of the protocol stack for PCI Express. The Intel® Stratix® 10 Hard IP for PCIe is a complete PCIe solution that includes the Transaction, Data Link, and PHY/MAC layers. The Hard IP solution contains dedicated hard logic that connects to the transceiver PHY interface. Each transceiver tile contains a PCIe Hard IP block supporting PCIe Gen1, Gen2, or Gen3 protocols with x1, x2, x4, x8, and x16 configurations. x1, x2, and x4 configurations result in unusable channels. The Hard IP resides at the bottom of the tile, and is 16 channels high. Additionally, the block includes extensible VF (Virtual Functions) interface to enable implementation of up to 2K VFs via the SRIOV-w (Single-Root I/O Virtualization) bridge. The following table and figure show the possible PCIe Hard IP channel configurations, the number of unusable channels, and the number of channels available for other protocols.
PCIe Hard IP Configuration | Number of Unusable Channels | Number of Channels Available for Other Protocols |
---|---|---|
PCIe x1 | 7 | 16 |
PCIe x2 | 6 | 16 |
PCIe x4 | 4 | 16 |
PCIe x8 | 0 | 16 |
PCIe x16 | 0 | 8 |
The table below maps all transceiver channels to PCIe Hard IP channels in available tiles.
Tile Channel Sequence | PCIe Hard IP Channel | Index within I/O Bank | Bottom Left Tile Bank Number | Top Left Tile Bank Number | Bottom Right Tile Bank Number | Top Right Tile Bank Number |
---|---|---|---|---|---|---|
23 | — | 5 | 1F | 1N | 4F | 4N |
22 | — | 4 | 1F | 1N | 4F | 4N |
21 | — | 3 | 1F | 1N | 4F | 4N |
20 | — | 2 | 1F | 1N | 4F | 4N |
19 | — | 1 | 1F | 1N | 4F | 4N |
18 | — | 0 | 1F | 1N | 4F | 4N |
17 | — | 5 | 1E | 1M | 4E | 4M |
16 | — | 4 | 1E | 1M | 4E | 4M |
15 | 15 | 3 | 1E | 1M | 4E | 4M |
14 | 14 | 2 | 1E | 1M | 4E | 4M |
13 | 13 | 1 | 1E | 1M | 4E | 4M |
12 | 12 | 0 | 1E | 1M | 4E | 4M |
11 | 11 | 5 | 1D | 1L | 4D | 4L |
10 | 10 | 4 | 1D | 1L | 4D | 4L |
9 | 9 | 3 | 1D | 1L | 4D | 4L |
8 | 8 | 2 | 1D | 1L | 4D | 4L |
7 | 7 | 1 | 1D | 1L | 4D | 4L |
6 | 6 | 0 | 1D | 1L | 4D | 4L |
5 | 5 | 5 | 1C | 1K | 4C | 4K |
4 | 4 | 4 | 1C | 1K | 4C | 4K |
3 | 3 | 3 | 1C | 1K | 4C | 4K |
2 | 2 | 2 | 1C | 1K | 4C | 4K |
1 | 1 | 1 | 1C | 1K | 4C | 4K |
0 | 0 | 0 | 1C | 1K | 4C | 4K |
The PCIe Hard IP block includes extensible VF (Virtual Functions) interface to enable the implementation of up to 2K VFs via the SRIOV-2 (Single-Root I/O Virtualization) bridge.
In network virtualization, single root input/output virtualization or SR-IOV is a network interface that allows the isolation of the PCI Express resources for manageability and performance reasons. A single physical PCI Express is shared on a virtual environment using the SR-IOV specification. The SR-IOV specification offers different virtual functions to different virtual components, such as a network adapter, on a physical server machine.
1.4. Overview Revision History
Document Version | Changes |
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2021.03.29 |
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2020.10.22 | Made the following change:
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2020.10.05 | Made the following changes:
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2020.03.03 | Made the following changes:
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2019.03.22 | Made the following change:
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2018.07.06 | Made the following changes:
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2018.03.16 | Made the following changes:
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2017.08.11 | Made the following changes:
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2017.06.06 | Made the following changes:
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2017.03.08 | Made the following changes:
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2017.02.17 | Made the following changes:
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2016.12.21 | Initial release. |
2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile
2.1. Transceiver Design IP Blocks
The following figure shows all the design blocks involved in designing and using Intel® Stratix® 10 transceivers.
2.2. Transceiver Design Flow
2.2.1. Select the PLL IP Core
Intel® Stratix® 10 transceivers have the following three types of PLL IP cores:
- Advanced Transmit (ATX) PLL IP core.
- Fractional PLL (fPLL) IP core.
- Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.
Select the appropriate PLL IP for your design. For additional details, refer to the PLLs and Clock Networks chapter.
Refer to Introduction to Intel FPGA IP Cores in the Intel® Quartus® Prime handbook for details on instantiating, generating and modifying IP cores.
2.2.2. Reset Controller
There are two methods to reset the transceivers in Intel® Stratix® 10 devices:
- Use the Intel® Stratix® 10 Transceiver PHY Reset Controller IP Core.
- Create your own reset controller that follows the recommended reset sequence.
2.2.3. Create Reconfiguration Logic
The Avalon® memory-mapped interface enables PLL and channel reconfiguration. You can dynamically adjust the PMA parameters, such as differential output voltage swing, and pre-emphasis settings. This adjustment can be done by writing to the Avalon® memory-mapped interface reconfiguration registers through the user-generated Avalon® memory-mapped interface master.
For detailed information on dynamic reconfiguration, refer to Reconfiguration Interface and Dynamic Reconfiguration chapter.
2.2.4. Connect the Native PHY IP Core to the PLL IP Core and Reset Controller
Connect the PHY IP, PLL IP core, and the reset controller. Write the top level module to connect all the IP blocks.
All of the I/O ports for each IP, can be seen in the <phy instance name>.v file or <phy instance name>.vhd, and in the <phy_instance_name>_bb.v file.
For more information about description of the ports, refer to the ports tables in the PLLs, Using the Transceiver Native PHY IP Core, and Resetting Transceiver Channels chapters.
2.2.5. Connect Datapath
- Assign FPGA pins to all the transceiver and reference clock I/O pins. For more details, refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines.
- All of the pin assignments set using the Pin Planner and the Assignment Editor are saved in the <top_level_project_name>.qsf file. You can also directly modify the Intel® Quartus® Prime Settings File (.qsf).
2.2.6. Modify Native PHY IP Core SDC
IP SDC is produced for any clock that reaches the FPGA fabric. In transceiver applications where the tx_clkouts and rx_clkouts (plus some more) are routed to the FPGA fabric, these clocks have SDC constraints on them in the Native PHY IP core.
2.2.7. Compile the Design
To compile the transceiver design, add the <phy_instancename>.ip files for all the IP blocks generated using the IP Catalog to the Intel® Quartus® Prime project library.
2.2.8. Verify Design Functionality
Simulate your design to verify the functionality of your design. For more details, refer to the Intel® Quartus® Prime Pro Edition User Guide: Debug Tools.
2.3. Configuring the Native PHY IP Core
Use the Native PHY IP core to configure the transceiver PHY for your protocol implementation. To instantiate the IP, select the Intel® Stratix® 10 device family, click Tools > IP Catalog to select your IP core variation. Use the Parameter Editor to specify the IP parameters and configure the PHY IP for your protocol implementation. To quickly configure the PHY IP, select a preset that matches your protocol configuration as a starting point. Presets are PHY IP configuration settings for various protocols that are stored in the IP Parameter Editor. Presets are explained in detail in the Presets section below.
You can also configure the PHY IP by selecting an appropriate Transceiver Configuration Rule. The transceiver configuration rules check the valid combinations of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings for any invalid settings.
Use the Native PHY IP core to instantiate one of the following PCS options:
- Standard PCS
- Enhanced PCS
- PCIe Gen3 PCS
- PCS Direct
Based on the Transceiver Configuration Rule that you select, the PHY IP core selects the appropriate PCS. Refer to the How to Place Channels for PIPE Configuration section or the PCIe solutions guides on restrictions on placement of transceiver channels next to active banks with PCI Express interfaces that are Gen3 capable.
After you configure the PHY IP core in the Parameter Editor, click Generate HDL to generate the IP instance. The top level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the PHY IP core to the PLL IP core, the reset controller IP core, and to other IP cores in your design.

2.3.1. Protocol Presets
To apply a preset to the Native PHY IP core, double-click the preset name. When you apply a preset, all relevant options and parameters are set in the current instance of the Native PHY IP core. For example, selecting the Interlaken preset enables all parameters and ports that the Interlaken protocol requires.
Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design. Any changes that you make are validated by the design rules for the transceiver configuration rules you specified, not the selected preset.
2.3.2. GXT Channels
Set the following parameters:
- Set the VCCR_GXB and VCCT_GXB supply voltage for the transceiver parameter to 1_1V.
- Set the TX channel bonding mode parameter to Not Bonded.
- Set the datarate parameter between 17400 and 25800 (L-Tile, and 28300 (H-Tile).
- Set the number of channels between 1 and 16.
Because each ATX PLL's tx_serial_clk_gt can connect up to 2 GXT channels, you must instantiate one to eight ATX PLLs. Be aware of the GXT channel location and connect the appropriate ATX PLL’s tx_serial_clk_gt port to the Native PHY IP Core's tx_serial_clk port.
Refer to Using the ATX PLL for GXT Channels section for more details.
Refer to AN 778: Intel® Stratix® 10 Transceiver Usage for more information about transceiver channel placement guidelines for both L- and H-Tiles.
2.3.3. General and Datapath Parameters
- General, Common PMA Options, and Datapath Options
- TX PMA
- RX PMA
- Standard PCS
- Enhanced PCS
- PCS Direct Datapath
- PCS-Core Interface
- Analog PMA Settings (Optional)
- Dynamic Reconfiguration
- Generation Options
Parameter | Value | Description |
---|---|---|
Message level for rule violations |
error warning |
Specifies the messaging level to use for parameter rule violations. Selecting error causes all rule violations to prevent IP generation. Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations. 6 |
Use fast reset for simulation | On/Off | When enabled, the IP disables reset staggering in simulation. The reset behavior in simulation is different from the reset behavior in the hardware. |
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver |
1_0V, 1_1V 7 |
Selects the VCCR_GXB and VCCT_GXB supply voltage for the transceiver. |
Transceiver Link Type | sr, lr | Selects the type of transceiver link. SR-Short Reach (Chip-to-chip communication), LR-Long Reach (Backplane communication). |
Transceiver channel type | GX, GXT | Specifies the transceiver channel variant. |
Transceiver configuration rules |
User Selection |
Specifies the valid configuration
rules for the transceiver. This parameter specifies the configuration rule against which the Parameter Editor checks your PMA and PCS parameter settings for specific protocols. Depending on the transceiver configuration rule selected, the Parameter Editor validates the parameters and options selected by you and generates error messages or warnings for all invalid settings. To determine the transceiver configuration rule to be selected for your protocol, refer to Transceiver Protocols using the Intel® Stratix® 10 H-Tile Transceiver Native PHY IP Core table for more details about each transceiver configuration rule. This parameter is used for rule checking and is not a preset. You need to set all parameters for your protocol implementation. Note: For a full description of the Transceiver
Configuration Rule Parameter Settings, refer to Table 12 in this section.
|
PMA configuration rules |
Basic SATA/SAS GPON |
Specifies the configuration rule for
the PMA. Select Basic for all other protocol modes except for SATA, and GPON. SATA (Serial ATA) can be used only if the Transceiver configuration rule is set to Basic/Custom (Standard PCS). Select GPON only if the Transceiver configuration rule is set to Basic (Enhanced PCS). |
Transceiver mode |
TX/RX Duplex TX Simplex RX Simplex |
Specifies the operational mode of the transceiver.
The default is TX/RX Duplex. |
Number of data channels | 1 – 24 |
Specifies the number of transceiver channels to be implemented. The default value is 1. |
Data rate | < valid transceiver datarate > |
Specifies the datarate in megabits per second (Mbps). |
Enable datapath and interface reconfiguration | On/Off |
When you turn this option on, you can preconfigure and dynamically switch between the Standard PCS, Enhanced PCS, and PCS direct datapaths. You cannot enable the simplified data interface option if you intend on using this feature to support channel reconfiguration. The default value is Off. |
Enable simplified data interface | On/Off |
By default, all 80-bits are ports for the tx_parallel_data and rx_parallel_data buses are exposed. You must understand the mapping of data and control signals within the interface. Refer to the Enhanced PCS TX and RX Control Ports section for details about mapping of data and control signals. When you turn on this option, the Native PHY IP core presents a simplified data and control interface between the FPGA fabric and transceiver. Only the sub-set of the 80-bits that are active for a particular FPGA fabric width are ports. You cannot enable simplified data interface when double rate transfer mode is enabled. The default value is Off. |
Enable double rate transfer mode | On/Off |
When selected, the Native PHY IP core splits the PCS parallel data into two words and each word is transferred to and from the transceiver interface at twice the parallel clock frequency and half the normal width of the fabric core interface. You cannot enable simplified data interface when double rate transfer mode is enabled. |
Enable PIPE EIOS RX Protection | On/Off |
This feature is available for Gen 2 and Gen 3 PCIe* PIPE interface selectable in Transceiver configuration rules. When selected, the Native PHY IP core improves the fault-tolerance and compatibility. You need to enable Enable dynamic reconfiguration and connect clock and reset. When selected,
Intel®
recommends using these commands to
enable physical simulation models:
|
Transceiver Configuration Setting | Description |
---|---|
Basic/Custom (Standard PCS) | Enforces a standard set of rules within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules. |
Basic/Custom w /Rate Match (Standard PCS) | Enforces a standard set of rules including rules for the Rate Match FIFO within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules. |
CPRI (Auto) | Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Auto. In Auto mode, the word aligner is set to deterministic latency. |
CPRI (Manual) | Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Manual. In Manual mode, logic in the FPGA fabric controls the word aligner. |
GbE | Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires. |
GbE 1588 | Enforces rules for the 1 GbE protocol with support for Precision time protocol (PTP) as defined in the IEEE 1588 Standard. |
Gen1 PIPE | Enforces rules for a Gen1 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer. |
Gen2 PIPE | Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer. |
Gen3 PIPE | Enforces rules for a Gen3 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer. |
Basic (Enhanced PCS) | Enforces a standard set of rules within the Enhanced PCS. Select these rules to implement protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules. |
Interlaken | Enforces rules required by the Interlaken protocol. |
10GBASE-R | Enforces rules required by the 10GBASE-R protocol. |
10GBASE-R 1588 | Enforces rules required by the 10GBASE-R protocol with 1588 enabled. This setting can also be used to implement CPRI protocol version 6.0 and later. |
10GBASE-R w/KR FEC | Enforces rules required by the 10GBASE-R protocol with KR FEC block enabled. |
40GBASE-R w/KR FEC | Enforces rules required by the 40GBASE-R protocol with the KR FEC block enabled. |
Basic w/KR FEC | Enforces a standard set of rules required by the Enhanced PCS when you enable the KR FEC block. Select this rule to implement custom protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules. |
PCS Direct | Enforces rules required by the PCS Direct mode. In this configuration the data flows through the PCS channel, but all the internal PCS blocks are bypassed. If required, the PCS functionality can be implemented in the FPGA fabric. |
2.3.4. PMA Parameters
- TX Bonding Options
- TX PLL Options
- TX PMA Optional Ports
- RX CDR Options
- RX PMA Optional Ports
Parameter | Value | Description |
---|---|---|
TX channel bonding mode |
Not bonded PMA only bonding PMA and PCS bonding |
Selects the bonding mode to be used for the channels specified. Bonded channels use a single TX PLL to generate a clock that drives multiple channels, reducing channel-to-channel skew. The following options are available: Not bonded: In a non-bonded configuration, only the high speed serial clock is expected to be connected from the TX PLL to the Native PHY IP core. The low speed parallel clock is generated by the local clock generation block (CGB) present in the transceiver channel. For non-bonded configurations, because the channels are not related to each other and the feedback path is local to the PLL, the skew between channels cannot be calculated. PMA only bonding: In PMA bonding, the high speed serial clock is routed from the transmitter PLL to the master CGB. The master CGB generates the high speed and low parallel clocks and the local CGB for each channel is bypassed. Refer to the Channel Bonding section for more details. PMA and PCS bonding : In a PMA and PCS bonded configuration, the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the network. The master CGB generates both the high and low speed clocks. The master channel generates the PCS control signals and distributes to other channels through a control plane block. The default value is Not bonded. Refer to Channel Bonding section in PLLs and Clock Networks chapter for more details. |
PCS TX channel bonding master | Auto, 0 to <number of channels> -1 |
This feature is only available if PMA and PCS bonding mode has been enabled. Specifies the master PCS channel for PCS bonded configurations. Each Native PHY IP core instance configured with bonding must specify a bonding master. If you select Auto, the Native PHY IP core automatically selects a recommended channel. The default value is Auto. Refer to the PLLs and Clock Networks chapter for more information about the TX channel bonding master. |
Actual PCS TX channel bonding master | 0 to <number of channels> -1 |
This parameter is automatically populated based on your selection for the PCS TX channel bonding master parameter. Indicates the selected master PCS channel for PCS bonded configurations. |
PCS reset sequence |
Independent Simultaneous |
Selects whether PCS tx/rx_digitalreset is asserted and deasserted
independently or simultaneously. Selecting independent staggers the
assertion and deassertion of the PCS reset of each transceiver channel
one after the other. The independent setting is recommended for PCS
non-bonded configurations. Selecting simultaneous, simultaneously
asserts and deasserts all the PCS resets of each transceiver channel.
Simultaneous setting is required for the following operations:
|
Parameter | Value | Description |
---|---|---|
TX local clock division factor |
1, 2, 4, 8 |
Specifies the value of the divider available in the transceiver channels to divide the TX PLL output clock to generate the correct frequencies for the parallel and serial clocks. |
Number of TX PLL clock inputs per channel |
1, 2, 3 , 4 |
Specifies the number of TX PLL clock inputs per channel. Use this parameter when you plan to dynamically switch between TX PLL clock sources. Up to four input sources are possible. |
Initial TX PLL clock input selection |
0 to <number of TX PLL clock inputs> -1 |
Specifies the initially selected TX PLL clock input. This parameter is necessary when you plan to switch between multiple TX PLL clock inputs. |
Parameter | Value | Description |
---|---|---|
Enable tx_pma_iqtxrx_clkout port | On/Off | Enables the optional tx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the TX PMA output clock to the input of a PLL. |
Enable tx_pma_elecidle port | On/Off | Enables the tx_pma_elecidle port. When you assert this port, the transmitter is forced into an electrical idle condition. This port has no effect when the transceiver is configured for PCI Express. |
Parameter | Value | Description |
---|---|---|
Number of CDR reference clocks | 1 - 5 |
Specifies the number of CDR reference clocks. Up to 5 sources are possible. The default value is 1. |
Selected CDR reference clock | 0 to <number of CDR reference clocks> -1 |
Specifies the initial CDR reference clock. This parameter determines the available CDR references used. The default value is 0. |
Selected CDR reference clock frequency | < datarate dependent > |
Specifies the CDR reference clock frequency. This value depends on the datarate specified. You should choose a lane datarate that results in a standard board oscillator reference clock frequency to drive the CDR reference clock and meet jitter requirements. Choosing a lane datarate that deviates from standard reference clock frequencies may result in custom board oscillator clock frequencies, which may be prohibitively expensive or unavailable. |
PPM detector threshold |
100 300 500 1000 |
Specifies the PPM threshold for the CDR. If the PPM between the incoming serial data and the CDR reference clock exceeds this threshold value, the CDR declares lose of lock. The default value is 1000. |
Parameters | Value | Description |
---|---|---|
Enable rx_pma_iqtxrx_clkout port | On/Off | Enables the optional rx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the RX PMA output clock to the input of a PLL. |
Enable rx_pma_clkslip port | On/Off | Enables the optional rx_pma_clkslip control input port. When asserted, causes the deserializer to either skip one serial bit or pauses the serial clock for one cycle to achieve word alignment. |
Enable rx_is_lockedtodata port | On/Off | Enables the optional rx_is_lockedtodata status output port. This signal indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream. This is an asynchronous output signal. |
Enable rx_is_lockedtoref port | On/Off | Enables the optional rx_is_lockedtoref status output port. This signal indicates that the RX CDR is currently locked to the CDR reference clock. This is an asynchronous output signal. |
Enable rx_set_lockedtodata port and rx_set_lockedtoref ports | On/Off | Enables the optional rx_set_lockedtodata and rx_set_lockedtoref control input ports. You can use these control ports to manually control the lock mode of the RX CDR. These are asynchronous input signals. |
Enable PRBS (Pseudo Random Bit Sequence) verifier control and status ports | On/Off | Enables the optional rx_prbs_err, rx_prbs_clr, and rx_prbs_done control ports. These ports control and collect status from the internal PRBS verifier. |
Enable rx_seriallpbken port | On/Off | Enables the optional rx_seriallpbken control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal. |
2.3.5. PCS-Core Interface Parameters
This section defines parameters available in the Native PHY IP core GUI to customize the PCS to core interface. The following table describes the available parameters. Based on the selection of the Transceiver Configuration Rule , if the specified settings violate the protocol standard, the Native PHY IP core Parameter Editor prints error or warning messages.
Parameter | Range | Description |
---|---|---|
General Interface Options | ||
Enable PCS reset status ports | On / Off | Enables the optional TX digital reset and RX digital reset release
status output ports including:
The PCS reset status ports help you to debug on why the transceiver native phy does not come out of reset. You can use these ports to debug common connectivity issues, such as the tx/rx_coreclkin being undriven, incorrect frequency, or FIFOs not being set properly. Please refer to the "Debugging with the PCS reset status ports" section for more detail. |
TX PCS-Core Interface FIFO | ||
TX Core Interface FIFO Mode |
Phase-Compensation Register Interlaken Basic |
The TX PCS FIFO is always operating in Phase
Compensation mode. The selection range specifies one of the
following modes for the TX Core FIFO:
Refer to the Special TX PCS Reset Release Sequence section to see if you need to implement a special reset release sequence in your top-level code. |
TX FIFO partially full threshold | 0-31 | Specifies the partially full threshold for the PCS TX Core FIFO. Enter the value at which you want the TX Core FIFO to flag a partially full status. |
TX FIFO partially empty threshold | 0-31 | Specifies the partially empty threshold for the PCS TX Core FIFO. Enter the value at which you want the TX Core FIFO to flag a partially empty status. |
Enable tx_fifo_full port | On / Off | Enables the tx_fifo_full port. This signal indicates when the TX Core FIFO is full. This signal is synchronous to tx_coreclkin. |
Enable tx_fifo_empty port | On / Off | Enables the tx_fifo_empty port. This signal indicates when the TX Core FIFO is empty. This is an asynchronous signal. |
Enable tx_fifo_pfull port | On / Off | Enables the tx_fifo_pfull port. This signal indicates when the TX Core FIFO reaches the specified partially full threshold. This signal is synchronous to tx_coreclkin. |
Enable tx_fifo_pempty port | On / Off | Enables the tx_fifo_pempty port. This signal indicates when the Core TX FIFO reaches the specified partially empty threshold. This is an asynchronous signal. |
Enable tx_dll_lock port | On/Off | Enables the transmit delay locked-loop port. This signal is synchronous to tx_clkout. |
RX PCS-Core Interface FIFO | ||
RX PCS-Core Interface FIFO Mode |
Phase-Compensation Phase-Compensation - Register Phase Compensation - Basic Register Register - Phase Compensation Register - Basic Interlaken 10GBASE-R |
Specifies one of the following modes for PCS RX FIFO:
Note: The fifo status flags are for Interlaken and
Basic mode only. They should be ignored in all other
cases.
|
RX FIFO partially full threshold | 0-63 | Specifies the partially full threshold for the PCS RX Core FIFO. The default value is 5. |
RX FIFO partially empty threshold | 0-63 | Specifies the partially empty threshold for the PCS RX Core FIFO. The default value is 2. |
Enable RX FIFO alignment word deletion (Interlaken) | On / Off | When you turn on this option, all alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion. |
Enable RX FIFO control word deletion (Interlaken) | On / Off | When you turn on this option, Interlaken control word removal is enabled. When the Enhanced PCS RX Core FIFO is configured in Interlaken mode, enabling this option, removes all control words after frame synchronization is achieved. Enabling this option requires that you also enable alignment word deletion. |
Enable rx_data_valid port | On / Off | Enables the rx_data_valid port. When asserted, this signal indicates when there is valid data on the RX parallel databus. |
Enable rx_fifo_full port | On / Off | Enables the rx_fifo_full port. This signal is required when the RX Core FIFO is operating in Interlaken or Basic mode and indicates when the RX Core FIFO is full. This is an asynchronous signal. |
Enable rx_fifo_empty port | On / Off | Enables the rx_fifo_empty port. This signal indicates when the RX Core FIFO is empty. This signal is synchronous to rx_coreclkin. |
Enable rx_fifo_pfull port | On / Off | Enables the rx_fifo_pfull port. This signal indicates when the RX Core FIFO has reached the specified partially full threshold that is set through the Native PHY IP core PCS-Core Interface tab. This is an asynchronous signal. |
Enable rx_fifo_pempty port | On / Off | Enables the rx_fifo_pempty port. This signal indicates when the RX Core FIFO has reached the specified partially empty threshold that is set through the Native PHY IP core PCS-Core Interface tab. This signal is synchronous to rx_coreclkin. |
Enable rx_fifo_del port (10GBASE‑R) | On / Off | Enables the optional rx_fifo_del status output port. This signal indicates when a word has been deleted from the RX Core FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This is an asynchronous signal. |
Enable rx_fifo_insert port (10GBASE‑R) | On / Off | Enables the rx_fifo_insert port. This signal indicates when a word has been inserted into the Core FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This signal is synchronous to rx_coreclkin. |
Enable rx_fifo_rd_en port | On / Off | Enables the rx_fifo_rd_en input port. This signal is enabled to read a word from the RX Core FIFO. This signal is synchronous to rx_coreclkin and is required when the RX Core FIFO is operating in Interlaken or Basic mode. |
Enable rx_fifo_align_clr port (Interlaken) | On / Off | Enables the rx_fifo_align_clr input port. Only used for Interlaken. This signal is synchronous to rx_clkout. |
Parameter | Range | Description |
---|---|---|
Selected tx_clkout clock source |
PCS clkout PCS clkout x2 pma_div_clkout |
Specifies the tx_clkout output port source. Data rate must be equal or higher than 5 Gbps if tx_pma_div_clkout is selected as the clock source for tx_clkout2. |
Enable tx_clkout2 port | On/ Off | Enables the tx_clkout2 port. |
Selected tx_clkout2 clock source |
PCS clkout PCS clkout x2 pma_div_clkout |
You must enable tx_clkout2 port in order to make a selection for this parameter.
Specifies the tx_clkout2 output port source. |
TX pma_div_clkout division factor |
Disabled 1, 2, 33, 40, 66 |
You must select the pma_div_clkout under selected tx_clkout clock source or tx_clkcout2 clock source option in order to enable a selection for this parameter.
Selects the divider that generates the appropriate pma_div_clkout frequency that the tx_clkout or tx_clkout2 ports use.
Example: For 10.3125 Gbps datarate, if the divider value 33 is selected, the pma_div_clkout resulting frequency is 156.25MHz. |
Selected tx_coreclkin clock network |
Dedicated Clock Global Clock |
Specifies the clock network used to drive the tx_coreclkin input.
Select “Dedicated Clock” if the tx_coreclkin input port is being driven by either tx/rx_clkout or tx/rx_clkout2 from the transceiver channel.
Select “Global Clock” if the tx_coreclkin input port is being driven by the Fabric clock network. You can also select “Global Clock” if tx_coreclkin is being driven by tx/rx_clkout or tx/rx_clkout2 via the Fabric clock network. |
Enable tx_coreclkin2 port | On/ Off | Enable this clock port to provide a fifo read clock when you have double rate transfer enabled with a PMA width of 20 without byte serialization. |
Parameter | Range | Description |
---|---|---|
Selected rx_clkout clock source |
PCS clkout PCS clkout x2 pma_div_clkout |
Specifies the rx_clkout output port source. |
Enable rx_clkout2 port | On/ Off | Enables the rx_clkout2 port. |
Selected rx_clkout2 clock source |
PCS clkout PCS clkout x2 pma_div_clkout |
You must enable rx_clkout2 port in order to make a selection for this parameter.
Specifies the rx_clkout2 output port source. |
RX pma_div_clkout division factor |
Disabled 1, 2, 33, 40, 66 |
You must select the pma_div_clkout under selected rx_clkout clock source or selected rx_clkcout2 clock source option in order to enable a selection for this parameter.
Selects the divider that generates the appropriate pma_div_clkout frequency that the rx_clkout port uses.
Example: For 10.3125Gbps datarate, if the divider value 33 is selected, the pma_div_clkout resulting frequency is 156.25MHz. |
Selected rx_coreclkin clock network |
Dedicated Clock Global Clock |
Specifies the clock network used to drive the rx_coreclkin input.
Select “Dedicated Clock” if the rx_coreclkin input port is being driven by either tx/rx_clkout or tx/rx_clkout2 from the transceiver channel.
Select “Global Clock” if the rx_coreclkin input port is being driven by the Fabric clock network. You can also select “Global Clock” if rx_coreclkin is being driven by tx/rx_clkout or tx/rx_clkout2 via the Fabric clock network. |
Parameter | Range | Description |
---|---|---|
Enable latency measurement ports | On/ Off |
Enables latency measurement ports: tx_fifo_latency_pulse, rx_fifo_latency_pulse tx_pcs_fifo_latency_pulse, rx_pcs_fifo_latency_pulse, latency_sclk |
2.3.6. Analog PMA Settings Parameters
In older device families, such as Intel® Arria® 10 and Stratix® V, you can only set the analog PMA settings through the Assignment Editor or the Quartus Settings File (QSF). However, for Intel® Stratix® 10 transceivers, you can also set them through the Native PHY IP Parameter Editor. There is also an option to provide sample QSF assignments for the settings chosen through the Native PHY IP Parameter Editor. Use this method when you need to modify one or two individual settings, or want to modify the settings without regenerating the IP.
You can specify values for the following types of analog PMA settings parameters in the Native PHY IP Parameter Editor:
- TX analog PMA settings:
- TX PMA analog mode rules
- Output swing level (VOD)
- Use default TX PMA analog settings
- Pre-emphasis first pre-tap polarity
- Pre-emphasis first pre-tap magnitude
- Pre-emphasis first post-tap polarity
- Pre-emphasis first post-tap magnitude
- Slew rate control
- On-chip termination
- High-speed compensation
- RX analog PMA settings:
- Use default RX PMA analog settings
- RX adaptation mode
- CTLE AC Gain
- CTLE EQ Gain
- VGA DC Gain
- RX on-chip termination
The following settings can not be set through the Native PHY IP Parameter Editor. You must set these through the Intel® Quartus® Prime Pro Edition Assignment Editor:
- REFCLK I/O Standard
- REFCLK Termination
- TX serial pin I/O Standard
- RX serial pin I/O Standard
To improve performance, Intel® Stratix® 10 FPGAs use a High Speed Differential I/O. Select High Speed Differential I/O as the I/O standard for the Intel® Stratix® 10 transmitter and receiver pins in the Intel® Quartus® Prime Pro Edition Assignment Editor or Quartus Settings File (.qsf). The pin assignments in the .qsf always take precedence over the settings selected in the Native PHY IP Parameter Editor.
The syntax is as follows:
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to <serial TX/RX pin name> -entity <name of the top-level file>
Refer to the Dedicated Reference Clock Settings section for details on the I/O standard and termination settings for the dedicated reference clock.
- Ok means that the assignment is recognized; thus, the Intel® Quartus® Prime Pro Edition fitter compilation uses the assignment.
- ? means that the assignment is not recognized; thus, the Intel® Quartus® Prime Pro Edition fitter compilation ignores the assignment.

Parameter | Value | Description |
---|---|---|
TX PMA analog mode rules | User Selection (cei_11100_lr to xfp_9950) | Selects the analog protocol mode to pre-select the TX pin swing settings (VOD, Pre-emphasis, and slew rate). After loading the pre-selected values in the GUI, if one or more of the individual TX pin swing settings need to be changed, then select the Provide sample QSF assignments option to modify the settings through the QSF. |
Use default TX PMA analog settings | On/Off | Selects whether to use default or custom TX PMA analog settings. |
Output Swing Level (VOD) | 17 to 31 | Selects the transmitter programmable output differential voltage
swing. (Use the
Intel®
Stratix® 10
L-Tile/H-Tile Pre-emphasis and Output Swing Estimator to see how changing VOD
affects your signal.) Note: Although the GUI displays a range of 0-31, you must not select values lower than
17.
Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_vod_output_swing_ctrl=<value>" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_powermode_ac_tx_vod_no_jitcomp = TX_VOD_NO_JITCOMP_AC_L0" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_powermode_dc_tx_vod_no_jitcomp = powerdown_tx_vod_no_jitcomp" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_powermode_ac_tx_vod_w_jitcomp = TX_VOD_W_JITCOMP_AC_L20" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_powermode_dc_tx_vod_w_jitcomp= TX_VOD_W_JITCOMP_DC_L20" -to <serial TX pin name> Note: For powerdown_tx_vod_no_jitcomp, if the reference
clock is paused or not available during operation, both TX buffer positive and
negative pins are equal to the TX output common mode voltage (VOCM). For the VOCM
value, refer to the
Intel®
Stratix® 10
Device Data Sheet.
|
Pre-Emphasis First Pre-Tap Polarity |
neg (-) pos (+) |
Selects the polarity of the first pre-tap for pre-emphasis. (Use
the
Intel®
Stratix® 10 L-Tile/H-Tile
Pre-emphasis and Output Swing Estimator to see how changing pre-emphasis
affects your signal.) Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_pre_emp_sign_pre_tap_1t=fir_pre_1t_<value>" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_powermode_ac_pre_tap = TX_PRE_TAP_AC_ON" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_powermode_dc_pre_tap = TX_PRE_TAP_DC_ON" -to <serial TX pin name> |
Pre-Emphasis First Pre-Tap Magnitude | 0 to 15 (0 to -6 dB gain for positive sign, and 0 to 6 dB gain for negative sign) | Selects the magnitude of the first pre-tap for pre-emphasis. (Use
the
Intel®
Stratix® 10 L-Tile/H-Tile
Pre-emphasis and Output Swing Estimator to see how changing pre-emphasis
affects your signal.) Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_pre_emp_switching_ctrl_pre_tap_1t=<value>" -to <serial TX pin name> |
Pre-Emphasis First Post-Tap Polarity |
neg (-) pos (+) |
Selects the polarity of the first post-tap for pre-emphasis. (Use
the
Intel®
Stratix® 10 L-Tile/H-Tile
Pre-emphasis and Output Swing Estimator to see how changing pre-emphasis
affects your signal.) Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_pre_emp_sign_1st_post_tap=fir_post_1t_<value>" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_compensation_posttap_en=enable" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_compensation_en=enable" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_powermode_ac_post_tap = TX_POST_TAP_W_JITCOMP_AC_ON" -to <serial TX pin name> set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_powermode_dc_post_tap = TX_POST_TAP_W_JITCOMP_DC_ON" -to <serial TX pin name> |
Pre-Emphasis First Post -Tap Magnitude | 0 to 24 (0 to -14 dB gain for positive sign, and 0 to 14 dB gain for negative sign) | Selects the magnitude of the first post-tap for pre-emphasis.
(Use the
Intel®
Stratix® 10 L-Tile/H-Tile
Pre-emphasis and Output Swing Estimator to see how changing pre-emphasis
affects your signal.) Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_pre_emp_switching_ctrl_1st_post_tap=<value>" -to <serial TX pin name> |
Slew Rate Control | 0 (slowest) - 5 (fastest) | Selects the slew rate of the TX output signal. Valid values span
from slowest to the fastest rate. Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_slew_rate_ctrl=slew_r<value>" -to <serial TX pin name> |
On-Chip Termination |
|
Selects the on-chip TX differential termination according to the
on-board trace impedance at the TX output pin. Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_term_sel=<value>" -to <serial TX pin name> |
High Speed Compensation | enable/disable | Enables the power-distribution network (PDN) induced
inter-symbol interference (ISI) compensation in the TX driver. When enabled, it
reduces the PDN- induced ISI jitter, but increases the power consumption. Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_tx_buf_compensation_en=<value>" -to <serial TX pin name> disable is only for PCIe* Gen1 and Gen2 mode. Refer to the "Parameters for the Native PHY IP Core in PIPE Gen1, Gen2, Gen3 Modes - Analog PMA Settings" table for details. |
Parameter | Value | Description |
---|---|---|
RX PMA analog mode rules | User Selection (analog_off to user_custom) | Selects the analog protocol mode rules to pre-select the RX pin swing settings (VOD, Pre-emphasis, and Slew Rate). |
Use default RX PMA analog settings | On/Off | Selects whether to use default or custom RX PMA analog
settings. Note: When you disable this setting by selecting Off, you should select one of the available options
in the Native PHY IP Parameter Editor as the PMA analog settings.
|
RX adaptation mode |
|
Select manual CTLE if you intend to tune the analog front end of all the transceiver channels by sweeping combinations of the TX and RX EQ parameters together. Select one of the adaptive modes based on your system loss characteristics if you intend to use the Adaptation engine in the RX PMA. Only use ctle_dfe_mode_2 for PCIe Gen3. When using any of the adaptive modes, refer to the PMA Functions section for more information about how to reconfigure across modes, and how to start and stop adaptation. |
RX On-chip Termination |
Supported:
Unsupported:
|
Specifies the on-chip termination value for the receiver according to the on-board trace impedance at the RX input pin. Note: To set RX On-chip Termination to OFF, use direct write via
Avalon® memory-mapped interface. Refer to the RX Bandwidth Selection table for the register address.
Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_rx_buf_term_sel=<value>" -to <serial RX pin name> |
CTLE AC Gain | 0 to 15 (-2 dB at the peak to +10 dB at the peak) |
Specifies the CTLE broadband gain. Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_rx_buf_ctle_ac_gain=<value>" -to <serial RX pin name> |
CTLE EQ Gain | 0 to 47 (0 dB to 16 dB) |
Specifies the CTLE equalization setting. Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_rx_buf_ctle_eq_gain=<value>" -to <serial RX pin name> |
VGA DC Gain | 0 to 31 ( -5 dB to +7 dB) | Specifies the VGA Gain for the receiver. Syntax: set_instance_assignment -name HSSI_PARAMETER "pma_rx_buf_vga_dc_gain=<value>" -to <serial RX pin name> |
Parameter | Value | Description |
---|---|---|
Provide sample QSF assignments | On/Off | Selects the option to provide QSF assignments to the above configuration, in case one or more individual values need to change. The sample QSF assignments list has different sets of attributes depending on the enabled blocks in the currently-selected analog PMA settings. |
2.3.7. Enhanced PCS Parameters
This section defines parameters available in the Native PHY IP core GUI to customize the individual blocks in the Enhanced PCS.
The following tables describe the available parameters. Based on the selection of the Transceiver Configuration Rule , if the specified settings violate the protocol standard, the Native PHY IP core Parameter Editor prints error or warning messages.
Parameter | Range | Description |
---|---|---|
Enhanced PCS / PMA interface width | 32, 40, 64 | Specifies the interface width between the Enhanced PCS and the PMA. |
FPGA fabric /Enhanced PCS interface width | 32, 40, 64, 66, 67 | Specifies the interface width between the Enhanced PCS
and the FPGA fabric. The 66-bit FPGA fabric to PCS interface width uses 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 66-bit word, with lower 2 bits from the control bus. The 67-bit FPGA fabric to PCS interface width uses the 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 67-bit word with lower 3 bits from the control bus. |
Enable 'Enhanced PCS' low latency mode | On/Off | Enables the low latency path for the Enhanced PCS. When you turn on this option, the individual functional blocks within the Enhanced PCS are bypassed to provide the lowest latency path from the PMA through the Enhanced PCS. When enabled, this mode is applicable for GX transceiver channels. Intel recommends not enabling it for GXT transceiver channels.. |
Parameter | Range | Description |
---|---|---|
Enable Interlaken frame generator | On / Off | Enables the frame generator block of the Enhanced PCS. |
Frame generator metaframe length | 5-8192 | Specifies the metaframe length of the frame generator. This metaframe length includes 4 framing control words created by the frame generator. |
Enable Frame Generator Burst Control | On / Off | Enables frame generator burst. This determines whether the frame generator reads data from the TX FIFO based on the input of port tx_enh_frame_burst_en. |
Enable tx_enh_frame port | On / Off | Enables the tx_enh_frame status output port. When the Interlaken frame generator is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal. |
Enable tx_enh_frame_diag_status port | On / Off | Enables the tx_enh_frame_diag_status 2‑bit input port. When the Interlaken frame generator is enabled, the value of this signal contains the status message from the framing layer diagnostic word. This signal is synchronous to tx_clkout. |
Enable tx_enh_frame_burst_en port | On / Off | Enables the tx_enh_frame_burst_en input port. When burst control is enabled for the Interlaken frame generator, this signal is asserted to control the frame generator data reads from the TX FIFO. This signal is synchronous to tx_clkout. |
Parameter | Range | Description |
---|---|---|
Enable Interlaken frame synchronizer | On / Off | When you turn on this option, the Enhanced PCS frame synchronizer is enabled. |
Frame synchronizer metaframe length | 5-8192 | Specifies the metaframe length of the frame synchronizer. |
Enable rx_enh_frame port | On / Off | Enables the rx_enh_frame status output port. When the Interlaken frame synchronizer is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal. |
Enable rx_enh_frame_lock port | On / Off | Enables the rx_enh_frame_lock output port. When the Interlaken frame synchronizer is enabled, this signal is asserted to indicate that the frame synchronizer has achieved metaframe delineation. This is an asynchronous output signal. |
Enable rx_enh_frame_diag_status port | On / Off | Enables therx_enh_frame_diag_status output port. When the Interlaken frame synchronizer is enabled, this signal contains the value of the framing layer diagnostic word (bits [33:32]). This is a 2 bit per lane output signal. It is latched when a valid diagnostic word is received. This is an asynchronous signal. |
Parameter | Range | Description |
---|---|---|
Enable Interlaken TX CRC-32 Generator | On / Off | When you turn on this option, the TX Enhanced PCS datapath enables the CRC32 generator function. CRC32 can be used as a diagnostic tool. The CRC contains the entire metaframe including the diagnostic word. |
Enable Interlaken TX CRC-32 generator error insertion | On / Off | When you turn on this option, the error insertion of the interlaken CRC-32 generator is enabled. Error insertion is cycle-accurate. When this feature is enabled, the assertion of tx_control[8] or tx_err_ins signal causes the CRC calculation during that word is incorrectly inverted, and thus, the CRC created for that metaframe is incorrect. |
Enable Interlaken RX CRC-32 checker | On / Off | Enables the CRC-32 checker function. |
Enable rx_enh_crc32_err port | On / Off | When you turn on this option, the Enhanced PCS enables the rx_enh_crc32_err port. This signal is asserted to indicate that the CRC checker has found an error in the current metaframe. This is an asynchronous signal. |
Parameter | Range | Description |
---|---|---|
Enable rx_enh_highber port (10GBASE‑R) | On / Off | Enables the rx_enh_highber port. For 10GBASE-R transceiver configuration rule, this signal is asserted to indicate a bit error rate higher than 10 -4 . Per the 10GBASE-R specification, this occurs when there are at least 16 errors within 125 μs. This is an asynchronous signal. |
Enable rx_enh_highber_clr_cnt port (10GBASE‑R) | On / Off | Enables the rx_enh_highber_clr_cnt input port. For the 10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of times the BER state machine has entered the "BER_BAD_SH" state. This is an asynchronous signal. |
Enable rx_enh_clr_errblk_count port (10GBASE‑R&FEC) | On / Off | Enables the rx_enh_clr_errblk_count input port. For the 10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of the times the RX state machine has entered the RX_E state. For protocols with FEC block enabled, this signal is asserted to reset the status counters within the RX FEC block. This is an asynchronous signal. |
Parameter | Range | Description |
---|---|---|
Enable TX 64b/66b encoder (10GBASE-R) | On / Off | When you turn on this option, the Enhanced PCS enables the TX 64b/66b encoder. |
Enable RX 64b/66b decoder (10GBASE-R) | On / Off | When you turn on this option, the Enhanced PCS enables the RX 64b/66b decoder. |
Enable TX sync header error insertion | On / Off | When you turn on this option, the Enhanced PCS supports cycle-accurate error creation to assist in exercising error condition testing on the receiver. When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly. If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded. |
Parameter | Range | Description |
---|---|---|
Enable TX scrambler (10GBASE-R/Interlaken) | On / Off | Enables the scrambler function. This option is available for the Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the scrambler in Basic (Enhanced PCS) mode when the block synchronizer is enabled and with 66:32, 66:40, or 66:64 gear box ratios. |
TX scrambler seed (10GBASE-R/Interlaken) | User‑specified 58-bit value | You must provide a non-zero seed for the Interlaken protocol. For a multi-lane Interlaken Transceiver Native PHY IP, the first lane scrambler has this seed. For other lanes' scrambler, this seed is increased by 1 per each lane. The initial seed for 10GBASE-R is 0x03FFFFFFFFFFFFFF. This parameter is required for the 10GBASE‑R and Interlaken protocols. |
Enable RX descrambler (10GBASE-R/Interlaken) | On / Off | Enables the descrambler function. This option is available for Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the descrambler in Basic (Enhanced PCS) mode with the block synchronizer enabled and with 66:32, 66:40, or 66:64 gear box ratios. |
Parameter | Range | Description |
---|---|---|
Enable Interlaken TX disparity generator | On / Off | When you turn on this option, the Enhanced PCS enables the disparity generator. This option is available for the Interlaken protocol. |
Enable Interlaken RX disparity checker | On / Off | When you turn on this option, the Enhanced PCS enables the disparity checker. This option is available for the Interlaken protocol. |
Enable Interlaken TX random disparity bit | On / Off | Enables the Interlaken random disparity bit. When enabled, a random number is used as disparity bit which saves one cycle of latency. |
Parameter | Range | Description |
---|---|---|
Enable RX block synchronizer | On / Off | When you turn on this option, the Enhanced PCS enables the RX block synchronizer. This options is available for the Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. |
Enable rx_enh_blk_lock port | On / Off | Enables the rx_enh_blk_lock port. When you enable the block synchronizer, this signal is asserted to indicate that the block delineation has been achieved. |
Parameter | Range | Description |
---|---|---|
Enable TX data bitslip | On / Off | When you turn on this option, the TX gearbox operates in bitslip mode. The tx_enh_bitslip port controls number of bits which TX parallel data slips before going to the PMA. |
Enable TX data polarity inversion | On / Off | When you turn on this option, the polarity of TX data is inverted. This allows you to correct incorrect placement and routing on the PCB. |
Enable RX data bitslip | On / Off | When you turn on this option, the Enhanced PCS RX block synchronizer operates in bitslip mode. When enabled, the rx_bitslip port is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the PCS. |
Enable RX data polarity inversion | On / Off | When you turn on this option, the polarity of the RX data is inverted. This allows you to correct incorrect placement and routing on the PCB. |
Enable tx_enh_bitslip port | On / Off | Enables the tx_enh_bitslip port. When TX bit slip is enabled, this signal controls the number of bits which TX parallel data slips before going to the PMA. |
Enable rx_bitslip port | On / Off | Enables the rx_bitslip port. When RX bit slip is enabled, the rx_bitslip signal is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the PCS. This port is shared between Standard PCS and Enhanced PCS. |
Parameter | Range | Description |
---|---|---|
Enable RX KR-FEC error marking | On/Off | When you turn on this option, the decoder asserts both sync bits (2'b11) when it detects an uncorrectable error. This feature increases the latency through the KR-FEC decoder. |
Error marking type | 10G, 40G | Specifies the error marking type (10G or 40G). |
Enable KR-FEC TX error insertion | On/Off | Enables the error insertion feature of the KR-FEC encoder. This feature allows you to insert errors by corrupting data starting a bit 0 of the current word. |
KR-FEC TX error insertion spacing | User Input (1 bit to 15 bit) | Specifies the spacing of the KR-FEC TX error insertion. |
Enable tx_enh_frame port | On/Off |
Enables the tx_enh_frame port. Asynchronous status flag output of the TX KR-FEC that signifies the beginning of the generated KR-FEC frame. |
Enable rx_enh_frame port | On/Off | Enables the rx_enh_frame port. Asynchronous status flag output of the RX KR-FEC that signifies the beginning of the received KR-FEC frame. |
Enable rx_enh_frame_diag_status port | On/Off | Enables the rx_enh_frame_diag_status
port. Asynchronous status flag output of the RX KR-FEC
that indicates the status of the current received KR-FEC frame.
|
2.3.8. Standard PCS Parameters
This section provides descriptions of the parameters that you can specify to customize the Standard PCS.
For specific information about configuring the Standard PCS for these protocols, refer to the sections of this user guide that describe support for these protocols.
Parameter | Range | Description |
---|---|---|
Standard PCS/PMA interface width |
8, 10, 16, 20 |
Specifies the data interface width between the Standard PCS and the transceiver PMA. |
FPGA fabric/Standard TX PCS interface width | 8, 10, 16, 20, 32, 40 | Shows the FPGA fabric to TX PCS interface width. This value is automatically determined by the current configuration of individual blocks within the Standard TX PCS datapath. |
FPGA fabric/Standard RX PCS interface width | 8, 10, 16, 20, 32, 40 | Shows the FPGA fabric to RX PCS interface width. This value is automatically determined by the current configuration of individual blocks within the Standard RX PCS datapath. |
Enable 'Standard PCS' low latency mode | On / Off | Enables the low latency path for the Standard PCS. Some of the functional blocks within the Standard PCS are bypassed to provide the lowest latency. You cannot turn on this parameter while using the Basic/Custom w/Rate Match (Standard PCS) specified for Transceiver configuration rules. |
Parameter | Range | Description |
---|---|---|
TX byte serializer mode |
Disabled Serialize x2 Serialize x4 |
Specifies the TX byte serializer mode for the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA serializer. The byte serializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Serialize x4 is only applicable for PCIe protocol implementation. |
RX byte deserializer mode |
Disabled Deserialize x2 Deserialize x4 |
Specifies the mode for the RX byte deserializer in the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA deserializer. The byte deserializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Deserialize x4 is only applicable for PCIe protocol implementation. |
Parameter | Range | Description |
---|---|---|
Enable TX 8B/10B encoder | On / Off | When you turn on this option, the Standard PCS enables the TX 8B/10B encoder. |
Enable TX 8B/10B disparity control | On / Off | When you turn on this option, the Standard PCS includes disparity control for the 8B/10B encoder. You can force the disparity of the 8B/10B encoder using the tx_forcedisp control signal. |
Enable RX 8B/10B decoder | On / Off | When you turn on this option, the Standard PCS includes the 8B/10B decoder. |
Parameter | Range | Description |
---|---|---|
RX rate match FIFO mode |
Disabled Basic 10-bit PMA Basic 20-bit PMAGbE PIPE PIPE 0ppm |
Specifies the operation of the RX rate match FIFO in the Standard PCS.
Rate Match FIFO in Basic (Single Width) Mode Rate Match FIFO Basic (Double Width) Mode Rate Match FIFO for GbE Transceiver Channel Datapath for PIPE |
RX rate match insert/delete -ve pattern (hex) | User-specified 20 bit pattern | Specifies the -ve (negative) disparity value for the RX rate match FIFO as a hexadecimal string. |
RX rate match insert/delete +ve pattern (hex) | User-specified 20 bit pattern | Specifies the +ve (positive) disparity value for the RX rate match FIFO as a hexadecimal string. |
Enable rx_std_rmfifo_full port | On / Off | Enables the optional rx_std_rmfifo_full port. |
Enable rx_std_rmfifo_empty port | On / Off | Enables the rx_std_rmfifo_empty port. |
PCI Express Gen3 rate match FIFO mode |
Bypass 0 ppm 600 ppm |
Specifies the PPM tolerance for the PCI Express Gen3 rate match FIFO. It is bypassed by default. |
Parameter | Range | Description |
---|---|---|
Enable TX bitslip | On / Off | When you turn on this option, the PCS includes the bitslip function. The outgoing TX data can be slipped by the number of bits specified by the tx_std_bitslipboundarysel control signal. |
Enable tx_std_bitslipboundarysel port | On / Off | Enables the tx_std_bitslipboundarysel control signal. |
RX word aligner mode |
bitslip manual (FPGA Fabric controlled) synchronous state machine deterministic latency |
Specifies the RX word aligner mode for the Standard PCS. The word
aligned width depends on the PCS and PMA width, and whether or not
8B/10B is enabled. Refer to "Word Aligner" for more information. |
RX word aligner pattern length |
7, 8, 10, 16, 20, 32, 40 |
Specifies the length of the pattern the word aligner uses for
alignment. Refer to "RX Word Aligner Pattern Length" table in "Word Aligner". It shows the possible values of "Rx Word Aligner Pattern Length" in all available word aligner modes. |
RX word aligner pattern (hex) | User-specified | Specifies the word alignment pattern up to 16 characters in hex. |
Number of word alignment patterns to achieve sync | 0-255 | Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock. The default is 3. |
Number of invalid words to lose sync | 0-63 | Specifies the number of invalid data codes or disparity errors that must be received before the word aligner loses synchronization. The default is 3. |
Number of valid data words to decrement error count | 0-255 | Specifies the number of valid data codes that must be received to decrement the error counter. If the word aligner receives enough valid data codes to decrement the error count to 0, the word aligner returns to synchronization lock. |
Enable fast sync status reporting for deterministic Latency SM | On / Off | When enabled, the rx_syncstatus asserts high immediately after the deserializer has completed slipping the bits to achieve word alignment. When it is not selected, rx_syncstatus asserts after the cycle slip operation is complete and the word alignment pattern is detected by the PCS (i.e. rx_patterndetect is asserted). This parameter is only applicable when the selected protocol is CPRI (Auto). |
Enable rx_std_wa_patternalign port | On / Off | Enables the rx_std_wa_patternalign port. When the word aligner is configured in manual mode and when this signal is enabled, the word aligner aligns to next incoming word alignment pattern. |
Enable rx_std_wa_a1a2size port | On / Off | Enables the optional rx_std_wa_a1a2size control input port. |
Enable rx_std_bitslipboundarysel port | On / Off | Enables the optional rx_std_bitslipboundarysel status output port. |
Enable rx_bitslip port | On / Off | Enables the rx_bitslip port. This port is shared between the Standard PCS and Enhanced PCS. |
Parameter | Range | Description |
---|---|---|
Enable TX bit reversal | On / Off |
When you turn on this option, the 8B/10B Encoder reverses TX parallel data before transmitting it to the PMA for serialization. The transmitted TX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. TX bit reversal ports are not available but can be changed via soft registers. RX bit reversal ports are available. |
Enable TX byte reversal | On / Off |
When you turn on this option, the 8B/10B Encoder reverses the byte order before transmitting data. This function allows you to reverse the order of bytes that were erroneously swapped. The PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS/PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration rules. TX byte reversal ports are not available but can be changed via soft registers. RX bit reversal ports are available. |
Enable TX polarity inversion | On / Off | When you turn on this option, the tx_std_polinv port controls polarity inversion of TX parallel data to the PMA. When you turn on this parameter, you also need to turn on the Enable tx_polinv port. |
Enable tx_polinv port | On / Off | When you turn on this option, the tx_polinv input control port is enabled. You can use this control port to swap the positive and negative signals of a serial differential link, if they were erroneously swapped during board layout. |
Enable RX bit reversal | On / Off | When you turn on this option, the word aligner
reverses RX parallel data. The received RX data bit order is reversed.
The normal order is LSB to MSB. The reverse order is MSB to LSB.
When you enable Enable RX bit reversal, you must also enable Enable rx_std_bitrev_ena port. |
Enable rx_std_bitrev_ena port | On / Off | When you turn on this option and assert the rx_std_bitrev_ena control port, the RX data order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. |
Enable RX byte reversal | On / Off | When you turn
on
this
option,
the word aligner reverses the byte
order,
before storing the data in the RX FIFO. This function allows you to
reverse the order of bytes that
are
erroneously swapped.
The
PCS can swap the ordering of either one of the 8- or 10-bit words,
when
the PCS / PMA interface width is 16
or 20
bits.
This option is not valid under certain
Transceiver configuration
rules.
When you enable Enable RX byte reversal, you must also select the Enable rx_std_byterev_ena port. |
Enable rx_std_byterev_ena port | On / Off | When you turn on this option and assert the rx_std_byterev_ena input control port, the order of the individual 8‑ or 10‑bit words received from the PMA is swapped. |
Enable RX polarity inversion | On / Off |
When you turn on this option, the rx_std_polinv port inverts the polarity of RX parallel data. When you turn on this parameter, you also need to enable Enable rx_polinv port. |
Enable rx_polinv port | On / Off | When you turn on this option, the rx_polinv input is enabled. You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout. |
Enable rx_std_signaldetect port | On / Off | When you turn on this option, the optional rx_std_signaldetect output port is enabled. This signal is required for the PCI Express protocol. If enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that you specified. |
Parameter | Range | Description |
---|---|---|
Enable PCIe dynamic datarate switch ports | On / Off | When you turn on this option, the pipe_rate, pipe_sw, and pipe_sw_done ports are enabled. You should connect these ports to the PLL IP core instance in multi-lane PCIe Gen2 and Gen3 configurations. The pipe_sw and pipe_sw_done ports are only available for multi-lane bonded configurations. |
Enable PCIe electrical idle control and status ports | On / Off | When you turn on this option, the pipe_rx_eidleinfersel and pipe_rx_elecidle ports are enabled. These ports are used for PCI Express configurations. |
Enable PCIe pipe_hclk_in and pipe_hclk_out ports | On / Off | When you turn on this option, the pipe_hclk_in, and pipe_hclk_out ports are enabled. These ports must be connected to the PLL IP core instance for the PCI Express configurations. |
2.3.9. PCS Direct Datapath Parameters
Parameter | Range | Description |
---|---|---|
PCS Direct interface width | 8, 10, 16, 20, 32, 40, 64 | Specifies the data interface width between the FPGA Fabric width and the transceiver PMA. |
2.3.10. Dynamic Reconfiguration Parameters
Each transceiver channel and PLL includes an Avalon® memory-mapped interface slave for reconfiguration. This interface provides direct access to the programmable address space of each channel and PLL. Because each channel and PLL includes a dedicated Avalon® memory-mapped interface slave, you can dynamically modify channels either concurrently or sequentially. If your system does not require concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.
You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths.
To enable Intel® Stratix® 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:
- Enable dynamic reconfiguration
- Enable Native PHY Debug Master Endpoint
- Enable capability registers
- Enable control and status registers
- Enable PRBS (Pseudo Random Binary Sequence) soft accumulators
Parameter | Value | Description |
---|---|---|
Enable dynamic reconfiguration | On/Off | When you turn on this option, the dynamic reconfiguration interface is enabled. |
Enable Native PHY Debug Master Endpoint | On/Off | When you turn on this option, the Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® memory-mapped interface slave for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel. |
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE | On/Off | When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the Enable control and status registers feature under Optional Reconfiguration Logic be enabled. |
Share reconfiguration interface | On/Off | When you turn on this option, the Transceiver Native PHY IP presents a single Avalon® memory-mapped interface slave for dynamic reconfiguration for all channels. In this configuration, the upper [n-1:11] address bits of the reconfiguration address bus specify the channel. The channel numbers are binary encoded. Address bits [10:0] provide the register offset address within the reconfiguration space for a channel. |
Enable rcfg_tx_digitalreset_release_ctrl port | On/Off | Enables the rcfg_tx_digitalreset_release_ctrl port that dynamically controls the TX PCS reset release sequence. This port usage is mandatory when reconfiguring to or from Enhanced PCS Configurations with TX PCS Gearbox ratios of either 32:67, 40:67, and 64:67. |
Parameter | Value | Description |
---|---|---|
Enable capability registers | On/Off | Enables capability registers that provide high level information about the configuration of the transceiver channel. |
Set user-defined IP identifier | User-defined | Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled. |
Enable control and status registers | On/Off | Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug. |
Enable PRBS (Pseudo Random Binary Sequence) soft accumulators | On/Off | Enables soft logic for performing PRBS bit and error accumulation when the hard PRBS generator and checker are used. |
Parameter | Value | Description |
---|---|---|
Configuration file prefix | <prefix> | Here, the file prefix to use for generated configuration files is specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files. |
Generate SystemVerilog package file | On/Off | When you turn on this option, the Transceiver Native PHY IP generates a SystemVerilog package file, reconfig_parameters.sv. This file contains parameters defined with the attribute values required for reconfiguration. |
Generate C header file | On/Off | When you turn on this option, the Transceiver Native PHY IP generates a C header file, reconfig_parameters.h. This file contains macros defined with the attribute values required for reconfiguration. |
Generate MIF (Memory Initialize File) | On/Off | When you turn on this option, the Transceiver Native PHY IP generates a MIF, reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format. |
Parameter | Value | Description |
---|---|---|
Enable multiple reconfiguration profiles | On/Off | When enabled, you can use the GUI to store multiple configurations. This information is used by Quartus to include the necessary timing arcs for all configurations during timing driven compilation. The Native PHY generates reconfiguration files for all of the stored profiles. The Native PHY also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them. Among other things this checks that you have exposed the same ports for each configuration.8 |
Enable embedded reconfiguration streamer | On/Off | Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles. This is optional and increases logic utilization. The PHY includes all of the logic and data necessary to dynamically reconfigure between pre-configured profiles. |
Generate reduced reconfiguration files | On/Off | When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles. The reconfiguration time decreases with the use of reduced .mif files. |
Number of reconfiguration profiles | 1-8 | Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled. |
Store current configuration to profile | 0-7 | Selects which reconfiguration profile to store/load/clear/refresh, when clicking the relevant button for the selected profile. |
Store configuration to selected profile | - | Clicking this button saves or stores the current Native PHY parameter settings to the profile specified by the Selected reconfiguration profile parameter. |
Load configuration from selected profile | - | Clicking this button loads the current Native PHY with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter. |
Clear selected profile | - | Clicking this button clears or erases the stored Native PHY parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY. |
Clear all profiles | - | Clicking this button clears the Native PHY parameter settings for all the profiles. |
Refresh selected profile | - | Clicking this button is equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the Native PHY parameter settings from stored profile specified by the Selected reconfiguration profile parameter and subsequently stores or saves the parameters back to the profile. |
2.3.11. Generation Options Parameters
Parameter | Value | Description |
---|---|---|
Generate parameter documentation file | On/Off | When you turn on this option, generation produces a Comma-Separated Value (.csv ) file with descriptions of the Transceiver Native PHY IP parameters. |
2.3.12. PMA, Calibration, and Reset Ports
In the following tables, the variables represent these parameters:
- <n>—The number of lanes
- <d>—The serialization factor
- <s>—The symbol size
- <p>—The number of PLLs
Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_serial_data[<n>-1:0] | Input | N/A |
This is the serial data output of the TX PMA. |
tx_serial_clk0 | Input | Clock | This is the serial clock from the TX PLL. The frequency of this clock depends on the datarate and clock division factor. This clock is for non bonded channels only. For bonded channels use the tx_bonding_clocks clock TX input. |
tx_bonding_clocks[<n><6>-1:0] | Input | Clock | This is a 6-bit bus which carries the low speed parallel clock per channel. These clocks are outputs from the master CGB. Use these clocks for bonded channels only. |
Optional Ports | |||
tx_serial_clk1
tx_serial_clk2 tx_serial_clk3 tx_serial_clk4 |
Inputs | Clocks |
These are the serial clocks from the TX PLL. These additional ports are enabled when you specify more than one TX PLL. |
tx_pma_iqtxrx_clkout | Output | Clock | This port is available if you turn on Enable tx_ pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the TX PMA output clock to the input of a PLL in the same tile. |
tx_pma_elecidle[<n>-1:0] | Input | Asynchronous
FSR9 |
When you assert this signal, the transmitter is forced to electrical idle. This port has no effect when you configure the transceiver for the PCI Express protocol. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_serial_data[<n>-1:0] | Input | N/A |
Specifies serial data input to the RX PMA. |
rx_cdr_refclk0 | Input | Clock |
Specifies reference clock input to the RX clock data recovery (CDR) circuitry. |
Optional Ports | |||
rx_cdr_refclk1– rx_cdr_refclk4 | Input | Clock |
Specifies reference clock inputs to the RX clock data recovery (CDR) circuitry. These ports allow you to change the CDR datarate. |
rx_pma_iqtxrx_clkout | Output | Clock | This port is available if you turn on Enable rx_ pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the RX PMA output clock to the input of a PLL. |
rx_pma_clkslip | Input | Clock
SSR9 |
When asserted, causes the deserializer to either skip one serial bit or pauses the serial clock for one cycle to achieve word alignment. |
rx_is_lockedtodata[<n>-1:0] | Output | rx_clkout |
When asserted, indicates that the CDR PLL is in locked-to-data mode. When continuously asserted and does not switch between asserted and deasserted, you can confirm that it is actually locked to data. |
rx_is_lockedtoref[<n>-1:0] | Output | rx_clkout |
When asserted, indicates that the CDR PLL is in locked-to-reference mode. |
rx_set_locktodata[<n>-1:0] | Input | Asynchronous |
This port provides manual control of the RX CDR circuitry. When asserted, the CDR switches to the lock-to-data mode. Refer to the Manual Lock Mode section for more details. |
rx_set_locktoref[<n>-1:0] | Input | Asynchronous |
This port provides manual control of the RX CDR circuitry. When asserted, the CDR switches to the lock-to-reference mode. Refer to the Manual Lock Mode section for more details. |
rx_prbs_done[<n>-1:0] | Output |
rx_coreclkin or rx_clkout
SSR9 |
When asserted, indicates the verifier has aligned and captured consecutive PRBS patterns and the first pass through a polynomial is complete. |
rx_prbs_err[<n>-1:0] | Output |
rx_coreclkin or rx_clkout
SSR9 |
When asserted, indicates an error only after the rx_prbs_done signal has been asserted. This signal gets asserted for three parallel clock cycles for every error that occurs. Errors can only occur once per word. |
rx_prbs_err_clr[<n>-1:0] | Input |
rx_coreclkin or rx_clkout
SSR9 |
When asserted, clears the PRBS pattern and deasserts the rx_prbs_done signal. |
rx_std_signaldetect[<n>-1:0] |
Output |
Asynchronous |
When enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage. This signal is required for the PCI Express, SATA and SAS protocols. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_seriallpbken[<n>-1:0] | Input |
Asynchronous SSR 10 |
This port is available if you turn on Enable rx_seriallpbken port in the Transceiver Native PHY IP core Parameter Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal can be enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_cal_busy[<n>-1:0] | Output | Asynchronous SSR9 |
When asserted, indicates that the initial TX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed. You must hold the channel in reset until calibration completes. |
rx_cal_busy[<n>-1:0] | Output | Asynchronous SSR9 |
When asserted, indicates that the initial RX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed. |
Name | Direction | Clock Domain11 | Description |
---|---|---|---|
tx_analogreset[<n>-1:0] | Input | Asynchronous | Resets the PMA TX portion of the transceiver PHY. |
tx_digitalreset[<n>-1:0] | Input | Asynchronous | Resets the PCS TX portion of the transceiver PHY.12 |
rx_analogreset[<n>-1:0] | Input | Asynchronous | Resets the PMA RX portion of the transceiver PHY. |
rx_digitalreset[<n>-1:0] | Input | Asynchronous | Resets the PCS RX portion of the transceiver PHY.13 |
tx_analogreset_stat [<n>-1:0] | Output | Asynchronous | TX PMA reset status port. |
rx_analogreset_stat [<n>-1:0] | Output | Asynchronous | RX PMA reset status port. |
tx_digitalreset_stat [<n>-1:0] | Output | Asynchronous | TX PCS reset status port. |
rx_digitalreset_stat [<n>-1:0] | Output | Asynchronous | RX PCS reset status port. |
tx_dll_lock | Output | Asynchronous | TX PCS delay locked loop status port. This port is available when the RX Core FIFO is operating in Interlaken or Basic mode. |
Optional Reset Port | |||
rcfg_tx_digitalreset_release_ctrl[<n>-1:0] 14 | Input | Asynchronous | This port usage is mandatory when reconfiguring to or from Enhanced PCS Configurations with TX PCS Gearbox ratios of either 67:32, 67:40, and 67:64. |
2.3.13. PCS-Core Interface Ports
- <n>—The number of lanes
- <d>—The serialization factor
- <s>— The symbol size
- <p>—The number of PLLs
Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_parallel_data[<n>80-1:0] |
Input |
Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout) |
TX parallel data inputs from the FPGA fabric to the TX PCS. If you select Enable simplified data interface in the Transceiver Native PHY IP core Parameter Editor, tx_parallel_data includes only the bits required for the configuration you specify. The data ports that are not active must be set to logical state zero. To determine which ports are active, refer to Transceiver PHY PCS-to-Core Interface Port Mapping section. |
unused_tx_parallel_data |
Input |
tx_clkout | Port is enabled, when you enable Enable simplified data interface. Connect all of these bits to 0. When Enable simplified data interface is not set, the unused bits are a part of tx_parallel_data. Refer to Transceiver PHY PCS-to-Core Interface Port Mapping to identify the ports you need to set to logical state zero. |
tx_control[<n><3>-1:0]
or tx_control[<n><8>-1:0] |
Input |
Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout) |
The tx_control ports have different functionality depending on the Enhanced PCS transceiver configuration rule selected. When Enable simplified data interface is not set, tx_control is part of tx_parallel_data. Refer to the Enhanced PCS TX and RX Control Ports section for more details. Refer to Transceiver PHY PCS-to-Core Interface Port Mapping section for port mappings of tx_control ports based on specific configurations. |
tx_word_marking_bit | Input | Synchronous to the clock driving the write side of the FIFO (tx_coreclkin ortx_clkout) |
This port is required if double rate transfer mode is enabled. A logic state of Zero on this port indicates the data on tx_parallel_data bus contains the Lower Significant Word. A logic state of One on this port indicates the data on tx_parallel_data bus contains the Upper Significant Word. Note that Enable simplified data interface must be disabled for double rate transfer mode to be enabled and therefore, tx_word_marking bit always appears as part of tx_parallel_data. Refer to Transceiver PHY PCS-to-Core Interface Port Mapping section for port mappings of tx_word_marking_bit. |
tx_coreclkin | Input | Clock |
The FPGA fabric clock. Drives the write side of the TX FIFO. For the Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32. Using frequency lower than this range can cause the TX FIFO to underflow and result in data corruption. |
tx_coreclkin2 | Input | Clock | Enable this clock port to provide a fifo read clock when you have double rate transfer enabled with a PMA width of 20 without byte serialization. |
tx_clkout |
Output |
Clock |
User has the option to select the clock source for this port between PCS clkout, PCS clkout x2, and pma_div_clkout. A valid clock source must be selected based on intended configuration. PCS clkout is a parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configurations. This clocks the blocks of the TX PCS. The frequency of this clock is equal to the datarate divided by PCS/PMA interface width. PCS clkout x2 is a parallel clock generated at twice the frequency of PCS clkout for double transfer rate mode configurations. The frequency of pma_div_clkout is the divided version of the TX PMA parallel clock. |
tx_clkout2 | Output | Clock |
User has the option to select the clock source for this port between PCS clkout, PCS clkout x2, and pma_div_clkout. A valid clock source must be selected based on intended configuration. In some cases, double rate transfer and bonding, for example, you may be required to enable this port for data transfer across the EMIB. PCS clkout is a parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configurations. This clocks the blocks of the TX PCS. The frequency of this clock is equal to the datarate divided by PCS/PMA interface width. PCS clkout x2 is a parallel clock generated at twice the frequency of PCS clkout for double transfer rate mode configurations. The frequency of pma_div_clkout is the divided version of the TX PMA parallel clock. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_parallel_data[<n>80-1:0] |
Output |
Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout) |
RX parallel data from the RX PCS to the FPGA fabric. If you select, Enable simplified data interface in the Transceiver Native PHY IP GUI, rx_parallel_data includes only the bits required for the configuration you specify. Otherwise, this interface is 80 bits wide. To determine which ports are active for specific transceiver configurations, refer to Transceiver PHY PCS-to-Core Interface Port Mapping. You can leave the unusual ports floating or not connected. |
unused_rx_parallel_data |
Output |
rx_clkout |
This signal specifies the unused data ports when you turn on Enable simplified data interface. When simplified data interface is not set, the unused ports are a part of rx_parallel_data. To determine which ports are active for specific transceiver configurations, refer to Transceiver PHY PCS-to-Core Interface Port Mapping. You can leave the unused data outputs floating or not connected. |
rx_control[<n> <8>-1:0] | Output |
Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout) |
The rx_control ports have different functionality depending on the Enhanced PCS transceiver configuration rule selected. When Enable simplified data interface is not set, rx_control is part of rx_parallel_data. Refer to the Enhanced PCS TX and RX Control Ports section for more details. To determine which ports are active for specific transceiver configurations, refer to Transceiver PHY PCS-to-Core Interface Port Mapping. |
rx_word_marking_bit | Output | Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout) |
This port is required if double rate transfer mode is enabled. A logic state of Zero on this port indicates the data on rx_parallel_data bus contains the Lower Significant Word. A logic state of One on this port indicates the data on rx_parallel_data bus contains the Upper Significant Word. Note that Enable simplified data interface must be disabled for double rate transfer mode to be enabled and therefore, rx_word_marking bit always appears as part of rx_parallel_data. Refer to Transceiver PHY PCS-to-Core Interface Port Mapping section for port mappings of rx_word_marking_bit. |
rx_coreclkin | Input | Clock |
The FPGA fabric clock. Drives the read side of the RX FIFO. For Interlaken protocol, the frequency of this clock could range from datarate/67 to datarate/32. |
rx_clkout |
Output |
Clock |
User has the option to select the clock source for this port between PCS clkout, PCS clkout x2, and pma_div_clkout. A valid clock source must be selected based on intended configuration. The PCS clkout is the low speed parallel clock recovered by the transceiver RX PMA, that clocks the blocks in the RX PCS. The frequency of this clock is equal to datarate divided by PCS/PMA interface width. PCS clkout x2 is a parallel clock generated at twice the frequency of PCS clkout for double transfer rate mode configurations. The frequency of pma_div_clkout is the divided version of the RX PMA parallel clock. |
rx_clkout2 | Output | Clock |
User has the option to select the clock source for this port between PCS clkout, PCS clkout x2, and pma_div_clkout. A valid clock source must be selected based on intended configuration. The PCS clkout is the low speed parallel clock recovered by the transceiver RX PMA, that clocks the blocks in the RX PCS. The frequency of this clock is equal to datarate divided by PCS/PMA interface width. PCS clkout x2 is a parallel clock generated at twice the frequency of PCS clkout for double transfer rate mode configurations. The frequency of pma_div_clkout is the divided version of the RX PMA parallel clock. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_fifo_wr_en[<n>-1:0] |
Input |
Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout) |
Assertion of this signal indicates that the TX data is valid. For Basic and Interlaken, you need to control this port based on TX Core FIFO flags so that the FIFO does not underflow or overflow. Refer to Enhanced PCS FIFO Operation for more details. |
tx_enh_data_valid[<n>-1:0] |
Input |
Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout) |
Assertion of this signal indicates that the TX data is valid. For transceiver configuration rules using 10GBASE-R, 10GBASE-R 1588, 10GBASE-R w/KR FEC, 40GBASE-R w/KR FEC, Basic w/KR FEC, or double rate transfer mode, you must control this signal based on the gearbox ratio. You must also use this signal instead of tx_fifo_wr_en whenever the transceiver Enhanced PCS gearbox is not set to a 1:1 ratio such as 66:40 or 64:32 as an example, except in the case of when the RX Core FIFO is configured in Interlaken or Basic mode in which case, you must use tx_fifo_wr_en instead. Refer to Enhanced PCS FIFO Operation for more details. |
tx_fifo_full[<n>-1:0] |
Output |
Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout) |
Assertion of this signal indicates the TX Core FIFO is full. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details. |
tx_fifo_pfull[<n>-1:0] |
Output |
Synchronous to the clock driving the write side of the FIFO tx_coreclkin or tx_clkout |
This signal gets asserted when the TX Core FIFO reaches its partially full threshold that is set through the Native PHY IP core PCS-Core Interface tab. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details. |
tx_fifo_empty[<n>-1:0] |
Output |
Asynchronous |
When asserted, indicates that the TX Core FIFO is empty. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details. |
tx_fifo_pempty[<n>-1:0] |
Output |
Asynchronous |
When asserted, indicates that the TX Core FIFO has reached its specified partially empty threshold that is set through the Native PHY IP core PCS-Core Interface tab. When you turn this option on, the Enhanced PCS enables the tx_fifo_pempty port, which is asynchronous. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_data_valid[<n>-1:0] |
Output |
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout |
When asserted, indicates that rx_parallel_data is valid. Discard invalid RX parallel data when rx_data_valid signal is low. Refer to Enhanced PCS FIFO Operation for more details. |
rx_enh_data_valid[<n>-1:0] |
Output |
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout |
When asserted, indicates that rx_parallel_data is valid. Discard invalid RX parallel data when rx_enh_data_valid is low. You must use this signal instead of rx_data_valid whenever the transceiver Enhanced PCS gearbox is not set to a 1:1 ratio such as 66:40 or 64:32 as an example, except in the case of when the RX Core FIFO is configured in Interlaken or Basic mode in which case, you must use rx_data_valid instead. Refer to Enhanced PCS FIFO Operation for more details. |
rx_fifo_full[<n>-1:0] |
Output |
Asynchronous |
When asserted, indicates that the RX Core FIFO is full. This signal gets asserted for 2 to 3 clock cycles.Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details. |
rx_fifo_pfull[<n>-1:0] |
Output |
Asynchronous |
When asserted, indicates that the RX Core FIFO has reached its specified partially full threshold. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details. |
rx_fifo_empty[<n>-1:0] |
Output |
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout |
When asserted, indicates that the RX Core FIFO is empty. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details. |
rx_fifo_pempty[<n>-1:0] |
Output |
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout |
When asserted, indicates that the RX Core FIFO has reached its specified partially empty threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details. |
rx_fifo_del[<n>-1:0] |
Output |
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout |
When asserted, indicates that a word has been deleted from the RX Core FIFO. This signal gets asserted for 2 to 3 clock cycles. This signal is used for the 10GBASE-R protocol. |
rx_fifo_insert[<n>-1:0] |
Output |
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout |
When asserted, indicates that a word has been inserted into the RX Core FIFO. This signal is used for the 10GBASE-R protocol. |
rx_fifo_rd_en[<n>-1:0] |
Input |
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout |
For RX Core FIFO Interlaken and Basic configurations, when this signal is asserted, a word is read from the RX Core FIFO. You need to control this signal based on RX Core FIFO flags so that the FIFO does not underflow or overflow. |
rx_fifo_align_clr[<n>-1:0] |
Input |
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout FSR 15 |
When asserted, the RX Core FIFO resets and begins searching for a new alignment pattern. This signal is only valid for the Interlaken protocol. Assert this signal for at least 4 cycles. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
latency_sclk | Input | clock | Latency measurement input reference clock. |
tx_fifo_latency_pulse | Output | tx_coreclkin | Latency pulse of TX core FIFO from latency measurement. |
tx_pcs_fifo_latency_pulse | Output | tx_clkout | Latency pulse of TX PCS FIFO from latency measurement. |
rx_fifo_latency_pulse | Output | rx_coreclkin | Latency pulse of RX core FIFO from latency measurement. |
rx_pcs_fifo_latency_pulse; | Output | rx_clkout | Latency pulse of RX PCS FIFO from latency measurement. |
2.3.14. Enhanced PCS Ports
In the following tables, the variables represent these parameters:
- <n>—The number of lanes
- <d>—The serialization factor
- <s>— The symbol size
- <p>—The number of PLLs
Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_enh_frame[<n>-1:0] | Output |
tx_clkout |
Asserted for 2 or 3 parallel clock cycles to indicate the beginning of a new metaframe. |
tx_err_ins | Input | tx_coreclkin |
For the Interlaken protocol, you can use this bit to insert the synchronous header and CRC32 errors if you have turned on Enable simplified data interface. When asserted, the synchronous header for that cycle word is replaced with a corrupted one. A CRC32 error is also inserted if Enable Interlaken TX CRC-32 generator error insertion is turned on. The corrupted sync header is 2'b00 for a control word, and 2'b11 for a data word. For CRC32 error insertion, the word used for CRC calculation for that cycle is incorrectly inverted, causing an incorrect CRC32 in the Diagnostic Word of the Metaframe. Note that a synchronous header error and a CRC32 error cannot be created for the Framing Control Words because the Frame Control Words are created in the frame generator embedded in TX PCS. Both the synchronous header error and the CRC32 errors are inserted if the CRC-32 error insertion feature is enabled in the Transceiver Native PHY IP Core GUI. |
tx_dll_lock | Output | tx_clkout | User should monitor this lock status when the TX Core FIFO is
configured in Interlaken or Basic mode of operation. For tx_dll_lock timing diagrams, refer to the Special TX PCS Reset Release Sequence under Resetting Transceiver Channels chapter. . |
tx_enh_frame_diag_status[2<n>-1:0] |
Input |
tx_clkout |
Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This message is inserted into the next diagnostic word generated by the frame generator block. This bus must be held constant for 5 clock cycles before and after the tx_enh_frame pulse. The following encodings are defined:
|
tx_enh_frame_burst_en[<n>-1:0] |
Input |
tx_clkout |
If Enable frame burst is enabled, this port controls frame generator data reads from the TX FIFO to the frame generator. It is latched once at the beginning of each Metaframe. If the value of tx_enh_frame_burst_en is 0, the frame generator does not read data from the TX FIFO for current Metaframe. Instead, the frame generator inserts SKIP words as the payload of Metaframe. When tx_enh_frame_burst_en is 1, the frame generator reads data from the TX FIFO for the current Metaframe. This port must be held constant for 5 clock cycles before and after the tx_enh_frame pulse. |
rx_enh_frame[<n>-1:0] |
Output |
rx_clkout |
When asserted, indicates the beginning of a new received Metaframe. This signal is pulse stretched. |
rx_enh_frame_lock[<n>-1:0] |
Output |
rx_clkout SSR16 |
When asserted, indicates the Frame Synchronizer state machine has achieved Metaframe delineation. This signal is pulse stretched. |
rx_enh_frame_diag_status[2 <n>-1:0] |
Output |
rx_clkout SSR16 |
Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This signal is latched when a valid diagnostic word is received in the end of the Metaframe while the frame is locked. The following encodings are defined:
|
rx_enh_crc32_err[<n>-1:0] |
Output |
rx_clkout FSR16 |
When asserted, indicates a CRC error in the current Metaframe. Asserted at the end of current Metaframe. This signal gets asserted for 2 or 3 cycles. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_enh_highber[<n>-1:0] | Output |
rx_clkout SSR16 |
When asserted, indicates a bit error rate that is greater than 10 -4. For the 10GBASE-R protocol, this BER rate occurs when there are at least 16 errors within 125 µs. This signal gets asserted for 2 to 3 clock cycles. |
rx_enh_highber_clr_cnt[<n>-1:0] |
Input |
rx_clkout SSR16 |
When asserted, clears the internal counter that indicates the number of times the BER state machine has entered the BER_BAD_SH state. |
rx_enh_clr_errblk_count[<n>-1:0] (10GBASE-R and FEC) |
Input |
rx_clkout SSR16 |
When asserted the error block counter resets to 0. Assertion of this signal clears the internal counter that counts the number of times the RX state machine has entered the RX_E state. In modes where the FEC block is enabled, the assertion of this signal resets the status counters within the RX FEC block. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_enh_blk_lock<n>-1:0] | Output |
rx_clkout SSR16 |
When asserted, indicates that block synchronizer has achieved block delineation. This signal is used for 10GBASE-R and Interlaken. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_bitslip[<n>-1:0] | Input |
rx_clkout SSR16 |
The rx_parallel_data slips 1 bit for every positive edge of the rx_bitslip input. Keep the rx_bitslip pulse high for at least 200 ns and each pulse 400 ns apart to ensure the data is slipped. The maximum shift is < pcswidth -1> bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits. |
tx_enh_bitslip[<n>-1:0] | Input |
rx_clkout
SSR16 |
The value of this signal controls the number of bits to slip the tx_parallel_data before passing to the PMA. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_enh_frame[<n>-1:0] | Output |
Asynchronous |
Asynchronous status flag output of TX KR-FEC that signifies the beginning of generated KR FEC frame |
rx_enh_frame[<n>-1:0] | Output |
rx_clkout
SSR16 |
Asynchronous status flag output of RX KR-FEC that signifies the beginning of received KR FEC frame |
rx_enh_frame_diag_status[2<n>-1:0] | Output |
rx_clkout
SSR16 |
Asynchronous status flag output of RX KR-FEC that indicates the status of the current received frame.
|
2.3.14.1. Enhanced PCS TX and RX Control Ports
When Enable simplified data interface is ON, all of the unused ports shown in the tables below, appear as a separate port. For example: It appears as unused_tx_control/ unused_rx_control port.
Enhanced PCS TX Control Port Bit Encodings
Name | Bit | Functionality | Description |
---|---|---|---|
tx_control | [1:0] | Synchronous header | The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. |
[2] | Inversion control | A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity. | |
[7:3] | Unused | ||
[8] | Insert synchronous header error or CRC32 | You can use this bit to insert synchronous header error or CRC32 errors. The functionality is similar to tx_err_ins. Refer to tx_err_ins signal description in Interlaken Frame Generator, Synchronizer and CRC32 table for more details. |
Name | Bit | Functionality |
---|---|---|
tx_control | [0] | XGMII control signal for parallel_data[7:0] |
[1] | XGMII control signal for parallel_data[15:8] | |
[2] | XGMII control signal for parallel_data[23:16] | |
[3] | XGMII control signal for parallel_data[31:24] | |
[4] | XGMII control signal for parallel_data[39:32] | |
[5] | XGMII control signal for parallel_data[47:40] | |
[6] | XGMII control signal for parallel_data[55:48] | |
[7] | XGMII control signal for parallel_data[63:56] | |
[8] | Unused |
Name | Bit | Functionality | Description |
---|---|---|---|
tx_control | [1:0] | Synchronous header | The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. |
[8:2] | Unused |
Name | Bit | Functionality | Description |
---|---|---|---|
tx_control | [1:0] | Synchronous header | The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. |
[2] | Inversion control | A logic low indicates that built-in disparity generator block in the Enhanced PCS maintains the running disparity. |
Enhanced PCS RX Control Port Bit Encodings
Name | Bit | Functionality | Description |
---|---|---|---|
rx_control | [1:0] | Synchronous header | The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. |
[2] | Inversion control | A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity. In the current implementation, this bit is always tied logic low (1'b0). | |
[3] | Payload word location | A logic high (1'b1) indicates the payload word location in a metaframe. | |
[4] | Synchronization word location | A logic high (1'b1) indicates the synchronization word location in a metaframe. | |
[5] | Scrambler state word location | A logic high (1'b1) indicates the scrambler word location in a metaframe. | |
[6] | SKIP word location | A logic high (1'b1) indicates the SKIP word location in a metaframe. | |
[7] | Diagnostic word location | A logic high (1'b1) indicates the diagnostic word location in a metaframe. | |
[8] | Synchronization header error, metaframe error, or CRC32 error status | A logic high (1'b1) indicates synchronization header error, metaframe error, or CRC32 error status. | |
[9] | Block lock and frame lock status | A logic high (1'b1) indicates that block lock and frame lock have been achieved. |
Name | Bit | Functionality |
---|---|---|
rx_control | [0] | XGMII control signal for parallel_data[7:0] |
[1] | XGMII control signal for parallel_data[15:8] | |
[2] | XGMII control signal for parallel_data[23:16] | |
[3] | XGMII control signal for parallel_data[31:24] | |
[4] | XGMII control signal for parallel_data[39:32] | |
[5] | XGMII control signal for parallel_data[47:40] | |
[6] | XGMII control signal for parallel_data[55:48] | |
[7] | XGMII control signal for parallel_data[63:56] | |
[9:8] | Unused |
Name | Bit | Functionality | Description |
---|---|---|---|
rx_control | [1:0] | Synchronous header | The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. |
[7:2] | Unused | ||
[9:8] | Unused |
Name | Bit | Functionality | Description |
---|---|---|---|
rx_control | [1:0] | Synchronous header | The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. |
[2] | Inversion control | A logic low indicates that built-in disparity generator block in the Enhanced PCS maintains the running disparity. |
2.3.15. Standard PCS Ports
In the following tables, the variables represent these parameters:
- <n>—The number of lanes
- <w>—The width of the interface
- <d>—The serialization factor
- <s>— The symbol size
- <p>—The number of PLLs
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_std_rmfifo_full[<n>-1:0] |
Output |
Asynchronous SSR17 |
Rate match FIFO full flag. When asserted the rate match FIFO is full. You must synchronize this signal. This port is only used for GigE mode. |
rx_std_rmfifo_empty[<n>-1:0] |
Output |
Asynchronous SSR17 |
Rate match FIFO empty flag. When asserted, match FIFO is empty. You must synchronize this signal. This port is only used for GigE mode. |
rx_rmfifostatus[<2*n>-1:0] |
Output |
Asynchronous |
Indicates FIFO status. The following encodings are defined:
If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_datak |
Input |
tx_clkout |
tx_datak is exposed if 8B/10B enabled and simplified data interface is set.When 1, indicates that the 8B/10B encoded word of tx_parallel_data is control. When 0, indicates that the 8B/10B encoded word of tx_parallel_data is data. For most configurations with simplified data interface disabled, tx_datak corresponds to tx_parallel_data[8]. For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Serializer is enabled, tx_datak corresponds to tx_parallel_data[8] and tx_parallel_data[19]. For PMA width of 20-bit with double rate transfer mode is disabled and Byte Serializer enabled, tx_datak corresponds to tx_parallel_data[8], tx_parallel_data[19], tx_parallel_data[48], and tx_parallel_data[59]. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus[1:0] corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
tx_forcedisp[<n>(<w>/<s>-1:0] |
Input |
Asynchronous |
tx_forcedisp is only exposed if 8B/10B, 8B/10B disparity control, and simplified data interface has been enabled. This signal allows you to force the disparity of the 8B/10B encoder. When "1", forces the disparity of the output data to the value driven on tx_dispval. When "0", the current running disparity continues. For most configurations with simplified data interface disabled, tx_forcedisp corresponds to tx_parallel_data[9]. For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Serializer is enabled, tx_forcedisp corresponds to tx_parallel_data[9] and tx_parallel_data[20]. For PMA width of 20-bit with double rate transfer mode is disabled and Byte Serializer enabled, tx_forcedisp corresponds to tx_parallel_data[9], tx_parallel_data[20], tx_parallel_data[49], and tx_parallel_data[60]. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
tx_dispval[<n>(<w>/<s>-1:0] |
Input |
Asynchronous |
tx_dispval is exposed if 8B/10B, 8B/10B disparity control, and simplified data interface has been enabled. Specifies the disparity of the data. When 0, indicates positive disparity, and when 1, indicates negative disparity. For most configurations with simplified data interface disabled, tx_dispval corresponds to tx_parallel_data[10]. For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Serializer is enabled, tx_forcedisp corresponds to tx_parallel_data[10] and tx_parallel_data[21]. For PMA width of 20-bit with double rate transfer mode is disabled and Byte Serializer enabled, tx_dispval corresponds to tx_parallel_data[10], tx_parallel_data[21], tx_parallel_data[50], and tx_parallel_data[61]. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
rx_datak[<n><w>/<s>-1:0] |
Output |
rx_clkout |
rx_datak is exposed if 8B/10B is enabled and simplified data interface is set. When 1, indicates that the 8B/10B decoded word of rx_parallel_data is control. When 0, indicates that the 8B/10B decoded word of rx_parallel_data is data. For most configurations with simplified data interface disabled, rx_datak corresponds to rx_parallel_data[8]. For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Serializer is enabled, rx_datak corresponds to rx_parallel_data[8] and rx_parallel_data[24]. For PMA width of 20-bit with double rate transfer mode is disabled and Byte Serializer enabled, rx_datak corresponds to rx_parallel_data[8], rx_parallel_data[24], rx_parallel_data[48], and tx_parallel_data[64]. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
rx_errdetect[<n><w>/<s>-1:0] | Output |
Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout) |
When asserted, indicates a code group violation detected on the received code group. Used along with rx_disperr signal to differentiate between code group violation and disparity errors. The following encodings are defined for rx_errdetect/rx_disperr:
If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
rx_disperr[<n><w>/<s>-1:0] | Output |
Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout) |
When asserted, indicates a disparity error on the
received code group. For most configurations with simplified data interface disabled, rx_disperr corresponds to rx_parallel_data[11]. For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_disperr corresponds to rx_parallel_data[11] and rx_parallel_data[27]. For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_disperr corresponds to rx_parallel_data[11], rx_parallel_data[27], rx_parallel_data[51], and rx_parallel_data[67]. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
rx_runningdisp[<n><w>/<s>-1:0] | Output |
Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout) |
When high, indicates that rx_parallel_data was received with negative disparity.
When low, indicates that rx_parallel_data was received with positive disparity. For most configurations with simplified data interface disabled, rx_runningdisp corresponds to rx_parallel_data[15]. For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_runningdisp corresponds to rx_parallel_data[15] and rx_parallel_data[31]. For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_runningdisp corresponds to rx_parallel_data[15], rx_parallel_data[31], rx_parallel_data[55], and rx_parallel_data[71]. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
rx_patterndetect[<n><w>/<s>-1:0] | Output | Asynchronous | When asserted, indicates that the programmed word
alignment pattern has been detected in the current word boundary. Refer to "Word Alignment Using the Standard PCS" section for more details. For most configurations with simplified data interface disabled, rx_patterndetect corresponds to rx_parallel_data[12]. For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_patterndetect corresponds to rx_parallel_data[12] and rx_parallel_data[28]. For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_patterndetect corresponds to rx_parallel_data[12], rx_parallel_data[28], rx_parallel_data[52], and rx_parallel_data[68]. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
rx_syncstatus[<n><w>/<s>-1:0] | Output | Asynchronous | When asserted, indicates that the conditions required
for synchronization are being met. Refer to "Word Alignment Using the Standard PCS" section for more details. rx_syncstatus is bus dependent on the width of the parallel data. For example, when the parallel data width is 32 bits, then rx_syncstatus is a 4 bit bus. The final expected value is 1'hf, indicating the control character is identified at the correct location in the 32 bit parallel word. For most configurations with simplified data interface disabled, rx_syncstatus corresponds to rx_parallel_data[10]. For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_syncstatus corresponds to rx_parallel_data[10] and rx_parallel_data[26]. For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_syncstatus corresponds to rx_parallel_data[10], rx_parallel_data[26], rx_parallel_data[50], and rx_parallel_data[66]. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_std_bitslipboundarysel[5 <n>-1:0] | Input |
Asynchronous SSR17 |
Bitslip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip. |
rx_std_bitslipboundarysel[5 <n>-1:0] | Output |
Synchronous to rx_clkout |
This port is used in deterministic latency word aligner mode. It reports the number of bits that the RX block slipped to achieve deterministic latency. |
rx_std_wa_patternalign[<n>-1:0] | Input |
Asynchronous SSR17 |
This port is enabled when you place the word aligner in manual mode. In manual mode, you align words by asserting rx_std_wa_patternalign. When the PCS-PMA Interface width is 10 bits, rx_std_wa_patternalign is level sensitive. For all the other PCS-PMA Interface widths, rx_std_wa_patternalign is positive edge sensitive. You can use this port only when the word aligner is configured in manual or deterministic latency mode. When the word aligner is in manual mode, and the PCS-PMA interface width is 10 bits, this is a level sensitive signal. In this case, the word aligner monitors the input data for the word alignment pattern, and updates the word boundary when it finds the alignment pattern. For all other PCS-PMA interface widths, this signal is edge sensitive.This signal is internally synchronized inside the PCS using the PCS parallel clock and should be asserted for at least 2 clock cycles to allow synchronization. |
rx_std_wa_a1a2size[<n>-1:0] | Input |
Asynchronous SSR17 |
Used for the SONET protocol. Assert when the A1 and A2 framing bytes must be detected. A1 and A2 are SONET framing alignment overhead bytes and are only used when the PMA data width is 8 or 16 bits. The 2 alignment markers valid status is captured in the 2 bit of rx_std_wa_ala2size signal. When both the markers are matched, then the value of the signal is 2'b11. If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations. |
rx_bitslip[<n>-1:0] | Input |
Asynchronous SSR17 |
Used when word aligner mode is bitslip mode. When the Word Aligner is in either Manual (FPGA Fabric width controlled), Synchronous State Machine or Deterministic Latency ,the rx_bitslip signal is not valid and should be tied to 0. For every rising edge of the rx_std_bitslip signal, the word boundary is shifted by 1 bit. Each bitslip removes the earliest received bit from the received data. |
Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_std_byterev_ena[<n>-1:0] |
Input |
Asynchronous SSR17 |
This control signal is available when the PMA width is 16 or 20 bits. When asserted, enables byte reversal on the RX interface. Use this when the MSB and LSB byte order of data packet from transmitter is inverted order than receiver. |
rx_std_bitrev_ena[<n>-1:0] |
Input |
Asynchronous SSR17 |
When asserted, enables bit reversal on the RX interface. Bit order may be reversed if external transmission circuitry transmits the most significant bit first. When enabled, the receiver receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner. |
tx_polinv[<n>-1:0] |
Input |
Asynchronous SSR17 |
When asserted, the TX polarity bit is inverted. Only active when TX bit polarity inversion is enabled. |
rx_polinv[<n>-1:0] |
Input |
Asynchronous SSR17 |
When asserted, the RX polarity bit is inverted. Only active when RX bit polarity inversion is enabled. |
2.3.16. Transceiver PHY PCS-to-Core Interface Reference Port Mapping
This section lists the following tables for the PCS-to-Core port interface mappings of all the supported configurations for the Enhanced PCS, Standard PCS, and PCS-Direct configurations when Simplified Data Interface is disabled or unavailable. For the port interface mappings for PCIe Gen1-Gen3, refer to the PCIe Express chapter. Refer to these tables when mapping certain port functions to tx_parallel_data and rx_parallel_data. The Intel® Stratix® 10L-/ H-Tile Transceiver PHY PCS-to-Core interface has a maximum 80-bit width parallel data bus per channel which includes data, control, word marker, PIPE, and PMA and PCS status ports depending on the PCS/datapath enabled and transceiver configurations.
2.3.16.1. PCS-Core Interface Ports: Enhanced PCS
TX Port Function | TX Port | RX Port Function | RX Port |
---|---|---|---|
Configuration-1, PMA Width-32, FPGA Fabric width-32 | |||
data[31:0] | tx_parallel_data[31:0] | data[31:0] | rx_parallel_data[31:0] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_prbs_err | rx_parallel_data[35] |
rx_prbs_done | rx_parallel_data[36] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-2, PMA Width-40, FPGA Fabric width-40 | |||
data[39:0] | tx_parallel_data[39:0] | data[39:0] | rx_parallel_data[39:0] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_data_valid | rx_parallel_data[79] |
Configuration-3, PMA Width-32/40/64, FPGA Fabric width-64/66/67 | |||
data[31:0] | tx_parallel_data[31:0] | data[31:0] | rx_parallel_data[31:0] |
data[63:32] | tx_parallel_data[71:40] | data[63:32] | rx_parallel_data[71:40] |
tx_control[3:0] | tx_parallel_data[35:32] | rx_control[3:0] | rx_parallel_data[35:32] |
tx_control[8:4] | tx_parallel_data[76:72] | rx_control[9:4] | rx_parallel_data[77:72] |
tx_enh_data_valid | tx_parallel_data[36] | rx_enh_data_valid | rx_parallel_data[36] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_data_valid | rx_parallel_data[79] |
TX Port Function | TX Port | RX Port Function | RX Port |
---|---|---|---|
Configuration-4, PMA Width-32, FPGA Fabric width-16 | |||
data[15:0] | tx_parallel_data[15:0] (lower word) | data[15:0] | rx_parallel_data[15:0] (lower word) |
data[31:16] | tx_parallel_data[15:0] (upper word) | data[31:16] | rx_parallel_data[15:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[19] (lower word) | rx_word_marking_bit=0 | rx_parallel_data[39] (upper word) |
tx_word_marking_bit=1 | tx_parallel_data[19] (upper word) | rx_word_marking_bit=1 | rx_parallel_data[39] (lower word) |
tx_fifo_wr_en | tx_parallel_data[79] (lower and upper word) | rx_data_valid | rx_parallel_data[79] (lower and upper word) |
Configuration-5, PMA Width-40, FPGA Fabric width-20 | |||
data[19:0] | tx_parallel_data[19:0] (lower word) | data[19:0] | rx_parallel_data[19:0] (lower word) |
data[39:20] | tx_parallel_data[19:0] (upper word) | data[39:20] | rx_parallel_data[19:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) |
tx_fifo_wr_en | tx_parallel_data[79] (lower and upper word) | rx_data_valid | rx_parallel_data[79] (lower and upper word) |
Configuration-6, PMA Width-32/40/64, FPGA Fabric width-32 | |||
data[31:0] | tx_parallel_data[31:0] (lower word) | data[31:0] | rx_parallel_data[31:0] (lower word) |
data[63:32] | tx_parallel_data[31:0] (upper word) | data[63:32] | rx_parallel_data[31:0] (upper word) |
tx_control[3:0] | tx_parallel_data[35:32] (lower word) | rx_control[3:0] | rx_parallel_data[35:32] (lower word) |
tx_control[8:4] | tx_parallel_data[36:32] (upper word) | rx_control[9:4] | rx_parallel_data[37:32] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) |
tx_enh_data_valid | tx_parallel_data[36] (lower and upper word) | rx_enh_data_valid | rx_parallel_data[36] (lower and upper word) |
tx_fifo_wr_en | tx_parallel_data[79] (lower and upper word) | rx_data_valid | rx_parallel_data[79] (lower and upper word) |
2.3.16.2. PCS-Core Interface Ports: Standard PCS
TX Port Function | TX Port | RX Port Function | RX Port |
---|---|---|---|
Configuration-7, PMA Width-8, 8B10B-NA, Byte Serializer-Disabled | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
rx_std_wa_a1a2size | rx_parallel_data[8] | ||
rx_syncstatus | rx_parallel_data[10] | ||
rx_patterndetect | rx_parallel_data[12] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-8, PMA Width-8, 8B10B-NA, Byte Serializer-Enabled | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
data[15:8] | tx_parallel_data[18:11] | data[15:8] | rx_parallel_data[23:16] |
rx_std_wa_a1a2size | rx_parallel_data[8], [24] | ||
rx_syncstatus | rx_parallel_data[10], [26] | ||
rx_patterndetect | rx_parallel_data[12], [28] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-9, PMA Width-10, 8B10B-Disabled, Byte Serializer-Disabled | |||
data[9:0] | tx_parallel_data[9:0] | data[9:0] | rx_parallel_data[9:0] |
rx_syncstatus | rx_parallel_data[10] | ||
rx_disperr | rx_parallel_data[11] | ||
rx_patterndetect | rx_parallel_data[12] | ||
rx_rmfifostatus[0] | rx_parallel_data[13] | ||
rx_rmfifostatus[1] | rx_parallel_data[14] | ||
rx_runningdisp | rx_parallel_data[15] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-10, PMA Width-10, 8B10B-Disabled, Byte Serializer-Enabled | |||
data[9:0] | tx_parallel_data[9:0] | data[9:0] | rx_parallel_data[9:0] |
data[19:10] | tx_parallel_data[20:11] | data[25:16] | rx_parallel_data[25:16] |
rx_syncstatus | rx_parallel_data[10], [26] | ||
rx_disperr | rx_parallel_data[11], [27] | ||
rx_patterndetect | rx_parallel_data[12], [28] | ||
rx_rmfifostatus[0] | rx_parallel_data[13], [29] | ||
rx_rmfifostatus[1] | rx_parallel_data[14], [30] | ||
rx_runningdisp | rx_parallel_data[15], [31] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-11, PMA Width-10, 8B10B-Enabled, Byte Serializer-Disabled | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
tx_datak | tx_parallel_data[8] | rx_datak | rx_parallel_data[8] |
tx_forcedisp | tx_parallel_data[9] | rx_errdetect | rx_parallel_data[9] |
tx_dispval | tx_parallel_data[10] | rx_syncstatus | rx_parallel_data[10] |
rx_disperr | rx_parallel_data[11] | ||
rx_patterndetect | rx_parallel_data[12] | ||
rx_rmfifostatus[0] | rx_parallel_data[13] | ||
rx_rmfifostatus[1] | rx_parallel_data[14] | ||
rx_runningdisp | rx_parallel_data[15] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-12, PMA Width-10, 8B10B-Enabled, Byte Serializer-Enabled | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
data[15:8] | tx_parallel_data[18:11] | data[15:8] | rx_parallel_data[23:16] |
tx_datak | tx_parallel_data[8], [19] | rx_datak | rx_parallel_data[8], [24] |
tx_forcedisp | tx_parallel_data[9], [20] | rx_errdetect | rx_parallel_data[9], [25] |
tx_dispval | tx_parallel_data[10], [21] | rx_syncstatus | rx_parallel_data[10], [26] |
rx_disperr | rx_parallel_data[11], [27] | ||
rx_patterndetect | rx_parallel_data[12], [28] | ||
rx_rmfifostatus[0] | rx_parallel_data[13], [29] | ||
rx_rmfifostatus[1] | rx_parallel_data[14], [30] | ||
rx_runningdisp | rx_parallel_data[15], [31] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-13, PMA Width-16, 8B10B-NA, Byte Serializer-Disabled | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
data[15:8] | tx_parallel_data[18:11] | data[15:8] | rx_parallel_data[23:16] |
rx_std_wa_a1a2size | rx_parallel_data[8], [24] | ||
rx_syncstatus | rx_parallel_data[10], [26] | ||
rx_patterndetect | rx_parallel_data[12], [28] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-14, PMA Width-16, 8B10B-NA, Byte Serializer-Enabled | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
data[15:8] | tx_parallel_data[18:11] | data[15:8] | rx_parallel_data[23:16] |
data[23:16] | tx_parallel_data[47:40] | data[23:16] | rx_parallel_data[47:40] |
data[31:24] | tx_parallel_data[58:51] | data[31:24] | rx_parallel_data[63:56] |
rx_std_wa_a1a2size | rx_parallel_data[8], [24], [48], [64] | ||
rx_syncstatus | rx_parallel_data[10], [26], [50], [66] | ||
rx_patterndetect | rx_parallel_data[12], [28], [52], [68] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-15, PMA Width-20, 8B10B-Disabled, Byte Serializer-Disabled | |||
data[9:0] | tx_parallel_data[9:0] | data[9:0] | rx_parallel_data[9:0] |
data[19:10] | tx_parallel_data[20:11] | data[19:10] | rx_parallel_data[25:16] |
rx_syncstatus | rx_parallel_data[10], [26] | ||
rx_disperr | rx_parallel_data[11], [27] | ||
rx_patterndetect | rx_parallel_data[12], [28] | ||
rx_rmfifostatus[0] | rx_parallel_data[13], [29] | ||
rx_rmfifostatus[1] | rx_parallel_data[14], [30] | ||
rx_runningdisp | rx_parallel_data[15], [31] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-16, PMA Width-20, 8B10B-Disabled, Byte Serializer-Enabled | |||
data[9:0] | tx_parallel_data[9:0] | data[9:0] | rx_parallel_data[9:0] |
data[20:11] | tx_parallel_data[20:11] | data[19:10] | rx_parallel_data[25:16] |
data[49:40] | tx_parallel_data[49:40] | data[29:20] | rx_parallel_data[49:40] |
data[60:51] | tx_parallel_data[60:51] | data[39:30] | rx_parallel_data[65:56] |
rx_syncstatus | rx_parallel_data[10], [26], [50], [66] | ||
rx_disperr | rx_parallel_data[11], [27], [51], [67] | ||
rx_patterndetect | rx_parallel_data[12], [28], [52], [68] | ||
rx_rmfifostatus[0] | rx_parallel_data[13], [29], [53], [69] | ||
rx_rmfifostatus[1] | rx_parallel_data[14], [30], [54], [70] | ||
rx_runningdisp | rx_parallel_data[15], [31], [55], [71] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-17, PMA Width-20, 8B10B-Enabled, Byte Serializer-Disabled | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
data[15:8] | tx_parallel_data[18:11] | data[15:8] | rx_parallel_data[23:16] |
tx_datak | tx_parallel_data[8], [19] | rx_datak | rx_parallel_data[8], [24] |
tx_forcedisp | tx_parallel_data[9], [20] | rx_errdetect | rx_parallel_data[9], [25] |
tx_dispval | tx_parallel_data[10], [21] | rx_syncstatus | rx_parallel_data[10], [26] |
rx_disperr | rx_parallel_data[11], [27] | ||
rx_patterndetect | rx_parallel_data[12], [28] | ||
rx_rmfifostatus[0] | rx_parallel_data[13], [29] | ||
rx_rmfifostatus[1] | rx_parallel_data[14], [30] | ||
rx_runningdisp | rx_parallel_data[15], [31] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-18, PMA Width-20, 8B10B-Enabled, Byte Serializer-Enabled | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
data[18:11] | tx_parallel_data[18:11] | data[15:8] | rx_parallel_data[23:16] |
data[23:16] | tx_parallel_data[47:40] | data[23:16] | rx_parallel_data[47:40] |
data[31:24] | tx_parallel_data[58:51] | data[31:24] | rx_parallel_data[63:56] |
tx_datak | tx_parallel_data[8], [19], [48], [59] | rx_datak | rx_parallel_data[8], [24], [48], [64] |
tx_forcedisp | tx_parallel_data[9], [20], [49], [60] | rx_errdetect | rx_parallel_data[9], [25], [49], [65] |
tx_dispval | tx_parallel_data[10], [21], [50], [61] | rx_syncstatus | rx_parallel_data[10], [26], [50], [66] |
rx_disperr | rx_parallel_data[11], [27], [51], [67] | ||
rx_patterndetect | rx_parallel_data[12], [28], [52], [68] | ||
rx_rmfifostatus[0] | rx_parallel_data[13], [29], [53], [69] | ||
rx_rmfifostatus[1] | rx_parallel_data[14], [30], [54], [70] | ||
rx_runningdisp | rx_parallel_data[15], [31], [55], [71] | ||
rx_data_valid | rx_parallel_data[79] |
TX Port Function | TX Port | RX Port Function | RX Port |
---|---|---|---|
Configuration-19, PMA Width-8, 8B10B-NA, Byte Serializer-Enabled | |||
data[7:0] | tx_parallel_data[7:0] (lower word) | data[7:0] | rx_parallel_data[7:0] (lower word) |
data[15:8] | tx_parallel_data[7:0] (upper word) | data[15:8] | rx_parallel_data[7:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | ||
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_syncstatus | rx_parallel_data[10] (lower and upper word) |
rx_patterndetect | rx_parallel_data[12] (lower and upper word) | ||
rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) | ||
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) | ||
Configuration-20, PMA Width-10, 8B10B-Disabled, Byte Serializer-Enabled | |||
data[9:0] | tx_parallel_data[9:0] (lower word) | data[9:0] | rx_parallel_data[9:0] (lower word) |
data[19:10] | tx_parallel_data[9:0] (upper word) | data[19:10] | rx_parallel_data[9:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_syncstatus | rx_parallel_data[10] (lower and upper word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_disperr | rx_parallel_data[11] (lower and upper word) |
rx_patterndetect | rx_parallel_data[12] (lower and upper word) | ||
rx_rmfifostatus[0] | rx_parallel_data[13] (lower and upper word) | ||
rx_rmfifostatus[1] | rx_parallel_data[14] (lower and upper word) | ||
rx_runningdisp | rx_parallel_data[15] (lower and upper word) | ||
rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) | ||
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) | ||
Configuration-21, PMA Width-10, 8B10B-Enabled, Byte Serializer-Enabled | |||
data[7:0] | tx_parallel_data[7:0] (lower word) | data[7:0] | rx_parallel_data[7:0] (lower word) |
data[15:8] | tx_parallel_data[7:0] (upper word) | data[15:8] | rx_parallel_data[7:0] (upper word) |
tx_datak | tx_parallel_data[8] (lower and upper word) | rx_datak | rx_parallel_data[8] (lower and upper word) |
tx_forcedisp | tx_parallel_data[9] (lower and upper word) | code_violation_status 18 | rx_parallel_data[9] (lower and upper word) |
tx_dispval | tx_parallel_data[10] (lower and upper word) | rx_syncstatus | rx_parallel_data[10] (lower and upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_disperr | rx_parallel_data[11] (lower and upper word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_patterndetect | rx_parallel_data[12] (lower and upper word) |
rx_rmfifostatus[0] | rx_parallel_data[13] (lower and upper word) | ||
rx_rmfifostatus[1] | rx_parallel_data[14] (lower and upper word) | ||
rx_runningdisp | rx_parallel_data[15] (lower and upper word) | ||
rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) | ||
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) | ||
Configuration-22, PMA Width-16, 8B10B-NA, Byte Serializer-Disabled | |||
data[7:0] | tx_parallel_data[7:0] (lower word) | data[7:0] | rx_parallel_data[7:0] (lower word) |
data[15:8] | tx_parallel_data[7:0] (upper word) | data[15:8] | rx_parallel_data[7:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | ||
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_syncstatus | rx_parallel_data[10] (lower and upper word) |
rx_patterndetect | rx_parallel_data[12] (lower and upper word) | ||
rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) | ||
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) | ||
Configuration-23, PMA Width-16, 8B10B-NA, Byte Serializer-Enabled | |||
data[7:0] | tx_parallel_data[7:0] (lower word) | data[7:0] | rx_parallel_data[7:0] (lower word) |
data[15:8] | tx_parallel_data[18:11] (lower word) | data[15:8] | rx_parallel_data[23:16] (lower word) |
data[23:16] | tx_parallel_data[7:0] (upper word) | data[23:16] | rx_parallel_data[7:0] (upper word) |
data[31:24] | tx_parallel_data[18:11] (upper word) | data[31:24] | rx_parallel_data[23:16] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | ||
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) |
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) | ||
Configuration-24, PMA Width-20, 8B10B-Disabled, Byte Serializer-Disabled | |||
data[9:0] | tx_parallel_data[9:0] (lower word) | data[9:0] | rx_parallel_data[9:0] (lower word) |
data[19:10] | tx_parallel_data[9:0] (upper word) | data[19:10] | rx_parallel_data[9:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_syncstatus | rx_parallel_data[10] (lower and upper word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_disperr | rx_parallel_data[11] (lower and upper word) |
rx_patterndetect | rx_parallel_data[12] (lower and upper word) | ||
rx_rmfifostatus[0] | rx_parallel_data[13] (lower and upper word) | ||
rx_rmfifostatus[1] | rx_parallel_data[14] (lower and upper word) | ||
rx_runningdisp | rx_parallel_data[15] (lower and upper word) | ||
rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) | ||
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) | ||
Configuration-25, PMA Width-20, 8B10B-Disabled, Byte Serializer-Enabled | |||
data[19:0] | tx_parallel_data[9:0], [20:11] (lower word) | data[19:0] | rx_parallel_data[9:0], [25:16] (lower word) |
data[39:20] | tx_parallel_data[9:0], [20:11] (upper word) | data[39:20] | rx_parallel_data[9:0], [25:16] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_syncstatus | rx_parallel_data[10], [26] (lower and upper word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_disperr | rx_parallel_data[11], [27] (lower and upper word) |
rx_patterndetect | rx_parallel_data[12], [28] (lower and upper word) | ||
rx_rmfifostatus[0] | rx_parallel_data[13], [29] (lower and upper word) | ||
rx_rmfifostatus[1] | rx_parallel_data[14], [30] (lower and upper word) | ||
rx_runningdisp | rx_parallel_data[15], [31] (lower and upper word) | ||
rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) | ||
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) | ||
Configuration-26, PMA Width-20, 8B10B-Enabled, Byte Serializer-Disabled | |||
data[7:0] | tx_parallel_data[7:0] (lower word) | data[7:0] | rx_parallel_data[7:0] (lower word) |
data[15:8] | tx_parallel_data[7:0] (upper word) | data[15:8] | rx_parallel_data[7:0] (upper word) |
tx_datak | tx_parallel_data[8] (lower and upper word) | rx_datak | rx_parallel_data[8] (lower and upper word) |
tx_forcedisp | tx_parallel_data[9] (lower and upper word) | code_violation_status 18 | rx_parallel_data[9] (lower and upper word) |
tx_dispval | tx_parallel_data[10] (lower and upper word) | rx_syncstatus | rx_parallel_data[10] (lower and upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_disperr | rx_parallel_data[11] (lower and upper word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_patterndetect | rx_parallel_data[12] (lower and upper word) |
rx_rmfifostatus[0] | rx_parallel_data[13] (lower and upper word) | ||
rx_rmfifostatus[1] | rx_parallel_data[14] (lower and upper word) | ||
rx_runningdisp | rx_parallel_data[15] (lower and upper word) | ||
rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) | ||
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) | ||
Configuration-27, PMA Width-20, 8B10B-Enabled, Byte Serializer-Enabled | |||
data[7:0] | tx_parallel_data[7:0] (lower word) | data[7:0] | rx_parallel_data[7:0] (lower word) |
data[15:8] | tx_parallel_data[18:11] (lower word) | data[15:8] | rx_parallel_data[23:16] (lower word) |
data[23:16] | tx_parallel_data[7:0] (upper word) | data[23:16] | rx_parallel_data[7:0] (upper word) |
data[31:24] | tx_parallel_data[18:11] (upper word) | data[31:24] | rx_parallel_data[23:16] (upper word) |
tx_datak | tx_parallel_data[8], [19] (lower and upper word) | rx_datak | rx_parallel_data[8], [24] (lower and upper word) |
tx_forcedisp | tx_parallel_data[9], [20] (lower and upper word) | code_violation_status 18 | rx_parallel_data[9], [25] (lower and upper word) |
tx_dispval | tx_parallel_data[10], [21] (lower and upper word) | rx_syncstatus | rx_parallel_data[10], [26] (lower and upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_disperr | rx_parallel_data[11], [27] (lower and upper word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_patterndetect | rx_parallel_data[12], [28] (lower and upper word) |
rx_rmfifostatus[0] | rx_parallel_data[13], [29] (lower and upper word) | ||
rx_rmfifostatus[1] | rx_parallel_data[14], [30] (lower and upper word) | ||
rx_runningdisp | rx_parallel_data[15], [31] (lower and upper word) | ||
rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) | ||
rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) | ||
rx_data_valid | rx_parallel_data[79] (lower and upper word) |
2.3.16.3. PCS-Core Interface Ports: PCS-Direct
TX Port Function | TX Port | RX Port Function | RX Port |
---|---|---|---|
Configuration-28, PMA Width-8, FPGA Fabric width-8 | |||
data[7:0] | tx_parallel_data[7:0] | data[7:0] | rx_parallel_data[7:0] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_data_valid | rx_parallel_data[79] |
Configuration-29, PMA Width-10, FPGA Fabric width-10 | |||
data[9:0] | tx_parallel_data[9:0] | data[9:0] | rx_parallel_data[9:0] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_data_valid | rx_parallel_data[79] |
Configuration-30, PMA Width-16, FPGA Fabric width-16 | |||
data[15:0] | tx_parallel_data[15:0] | data[15:0] | rx_parallel_data[15:0] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_data_valid | rx_parallel_data[79] |
Configuration-31, PMA Width-20, FPGA Fabric width-20 | |||
data[19:0] | tx_parallel_data[19:0] | data[19:0] | rx_parallel_data[19:0] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_data_valid | rx_parallel_data[79] |
Configuration-32, PMA Width-32, FPGA Fabric width-32 | |||
data[31:0] | tx_parallel_data[31:0] | data[31:0] | rx_parallel_data[31:0] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_prbs_err | rx_parallel_data[35] |
rx_prbs_done | rx_parallel_data[36] | ||
rx_data_valid | rx_parallel_data[79] | ||
Configuration-33, PMA Width-40, FPGA Fabric width-40 | |||
data[39:0] | tx_parallel_data[39:0] | data[39:0] | rx_parallel_data[39:0] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_data_valid | rx_parallel_data[79] |
Configuration-34, PMA Width-64, FPGA Fabric width-64 | |||
data[31:0] | tx_parallel_data[31:0] | data[31:0] | rx_parallel_data[31:0] |
data[63:32] | tx_parallel_data[71:40] | data[63:32] | rx_parallel_data[71:40] |
tx_fifo_wr_en | tx_parallel_data[79] | rx_data_valid | rx_parallel_data[79] |
TX Port Function | TX Port | RX Port Function | RX Port |
---|---|---|---|
Configuration-35, PMA Width-16, FPGA Fabric width-8 | |||
data[7:0] | tx_parallel_data[7:0] (lower word) | data[7:0] | rx_parallel_data[7:0] (lower word) |
data[15:8] | tx_parallel_data[7:0] (upper word) | data[15:8] | rx_parallel_data[7:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[19] (lower word) | rx_word_marking_bit=0 | rx_parallel_data[39] (upper word) |
tx_word_marking_bit=1 | tx_parallel_data[19] (upper word) | rx_word_marking_bit=1 | rx_parallel_data[39] (lower word) |
tx_fifo_wr_en | tx_parallel_data[79] (lower and upper word) | rx_data_valid | rx_parallel_data[79] |
Configuration-36, PMA Width-20, FPGA Fabric width-10 | |||
data[9:0] | tx_parallel_data[9:0] (lower word) | data[9:0] | rx_parallel_data[9:0] (lower word) |
data[19:10] | tx_parallel_data[9:0] (upper word) | data[19:10] | rx_parallel_data[9:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[19] (lower word) | rx_word_marking_bit=0 | rx_parallel_data[39] (upper word) |
tx_word_marking_bit=1 | tx_parallel_data[19] (upper word) | rx_word_marking_bit=1 | rx_parallel_data[39] (lower word) |
tx_fifo_wr_en | tx_parallel_data[79] (lower and upper word) | rx_data_valid | rx_parallel_data[79] |
Configuration-37, PMA Width-32, FPGA Fabric width-16 | |||
data[15:0] | tx_parallel_data[15:0] (lower word) | data[15:0] | rx_parallel_data[15:0] (lower word) |
data[31:16] | tx_parallel_data[15:0] (upper word) | data[31:16] | rx_parallel_data[15:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[19] (lower word) | rx_word_marking_bit=0 | rx_parallel_data[39] (upper word) |
tx_word_marking_bit=1 | tx_parallel_data[19] (upper word) | rx_word_marking_bit=1 | rx_parallel_data[39] (lower word) |
tx_fifo_wr_en | tx_parallel_data[79] (lower and upper word) | rx_data_valid | rx_parallel_data[79] |
Configuration-38, PMA Width-40, FPGA Fabric width-20 | |||
data[19:0] | tx_parallel_data[19:0] (lower word) | data[19:0] | rx_parallel_data[19:0] (lower word) |
data[39:20] | tx_parallel_data[19:0] (upper word) | data[39:20] | rx_parallel_data[19:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) |
tx_fifo_wr_en | tx_parallel_data[79] (lower and upper word) | rx_data_valid | rx_parallel_data[79] (lower and upper word) |
Configuration-39, PMA Width-64, FPGA Fabric width-32 | |||
data[31:0] | tx_parallel_data[31:0] (lower word) | data[31:0] | rx_parallel_data[31:0] (lower word) |
data[63:32] | tx_parallel_data[31:0] (upper word) | data[63:32] | rx_parallel_data[31:0] (upper word) |
tx_word_marking_bit=0 | tx_parallel_data[39] (lower word) | rx_word_marking_bit=0 | rx_parallel_data[39] (lower word) |
tx_word_marking_bit=1 | tx_parallel_data[39] (upper word) | rx_word_marking_bit=1 | rx_parallel_data[39] (upper word) |
tx_fifo_wr_en | tx_parallel_data[79] (lower and upper word) | rx_data_valid | rx_parallel_data[79] (lower and upper word) |
2.3.17. IP Core File Locations
When you generate your Transceiver Native PHY IP, the Intel® Quartus® Prime Pro Edition software generates the HDL files that define your instance of the IP. In addition, the Intel® Quartus® Prime Pro Edition software generates an example Tcl script to compile and simulate your design in the ModelSim simulator. It also generates simulation scripts for Synopsys VCS, Aldec Active-HDL, Aldec Riviera-Pro, and Cadence Incisive Enterprise.
The following table describes the directories and the most important files for the parameterized Transceiver Native PHY IP core and the simulation environment. These files are in clear text.
File Name | Description |
---|---|
<project_dir> | The top-level project directory. |
<your_ip_name> .v or .vhd | The top-level design file. |
<your_ip_name> .qip | A list of all files necessary for Intel® Quartus® Prime compilation. |
<your_ip_name> .bsf | A Block Symbol File (.bsf) for your Transceiver Native PHY instance. |
<project_dir>/<your_ip_name>/ | The directory that stores the HDL files that define the Transceiver Native PHY IP. |
<project_dir>/sim | The simulation directory. |
<project_dir>/sim/aldec | Simulation files for Riviera-PRO simulation tools. |
<project_dir>/sim/cadence | Simulation files for Cadence simulation tools. |
<project_dir>/sim/mentor | Simulation files for Mentor simulation tools. |
<project_dir>/sim/synopsys | Simulation files for Synopsys simulation tools. |
<project_dir>/synth | The directory that stores files used for synthesis. |
The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the following simulators:
- ModelSim SE
- Synopsys VCS MX
- Cadence NCSim
If you select VHDL for your transceiver PHY, only the wrapper generated by the Intel® Quartus® Prime Pro Edition software is in VHDL. All the underlying files are written in Verilog or SystemVerilog. To enable simulation using a VHDL-only ModelSim license, the underlying Verilog and SystemVerilog files for the Transceiver Native PHY IP are encrypted so that they can be used with the top-level VHDL wrapper without using a mixed-language simulator.
For more information about simulating with ModelSim, refer to Sourcing Mentor Graphics ModelSim Simulator Setup Scripts.
The Transceiver Native PHY IP cores do not support the NativeLink feature in the Intel® Quartus® Prime Pro Edition software.
2.4. Using the Intel Stratix 10 L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP Core
Use the Native PHY IP core to configure the transceiver PHY for your protocol implementation. To instantiate the IP, select the Intel® Stratix® 10 device family, click Tools > IP Catalog to select your IP core variation. Use the Parameter Editor to specify the IP parameters and configure the PHY IP for your protocol implementation. To quickly configure the PHY IP, select a preset that matches your protocol configuration as a starting point. Presets are PHY IP configuration settings for various protocols that are stored in the IP Parameter Editor. Presets are explained in detail in the Presets section below.
You can also configure the PHY IP by selecting an appropriate Transceiver Configuration Rule. The transceiver configuration rules check the valid combinations of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings for any invalid settings.
Use the Native PHY IP core to instantiate one of the following PCS options:
- Standard PCS
- Enhanced PCS
- PCIe Gen3 PCS
- PCS Direct
Based on the Transceiver Configuration Rule that you select, the PHY IP core selects the appropriate PCS. Refer to the How to Place Channels for PIPE Configuration section or the PCIe solutions guides on restrictions on placement of transceiver channels next to active banks with PCI Express interfaces that are Gen3 capable.
After you configure the PHY IP core in the Parameter Editor, click Generate HDL to generate the IP instance. The top level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the PHY IP core to the PLL IP core, the reset controller IP core, and to other IP cores in your design.
2.4.1. PMA Functions
2.4.1.1. TX PMA Use Model
You can configure all TX PMA settings using the Analog PMA Settings tab, or if needed, through the corresponding QSF assignments provided through the tab. You can also reconfigure them through the registers outlined in the Logical View of the L-Tile/H-Tile Transceiver Registers.
2.4.1.2. RX PMA Use Model
Adaptation is available for CTLE, VGA, and DFE. The RX PMA Adaptation Modes include:
- Manual CTLE, Manual VGA, DFE Off
- Adaptive CTLE, Adaptive VGA, DFE Off
- Adaptive CTLE, Adaptive VGA, All-Tap Adaptive DFE
- Adaptive CTLE, Adaptive VGA, 1-Tap Adaptive DFE
- ctle_dfe_mode_2 (Adaptive Mode for PCIe Gen3) — This mode fixes the AC gain and leaves everything else adaptive.
Analog PMA Setting | Range of Values |
---|---|
CTLE |
AC gain: 0-15 EQ gain: 0-47 |
VGA | 0-31 |
DFE (Adaptive only) |
Tap1: -63 to 63 Taps 2-3: -31 to 31 Taps 4-7: -15 to 15 Taps 8-15: -7 to 7 |
2.4.1.2.1. Using RX in Manual Mode
Contact Intel Support to obtain the recommended values for your system loss profile.
These values can always be overwritten through the Avalon® memory-mapped interface. The new values take precedence over values defined statically in the PHY IP core. Use this method to dynamically set values and avoid re-compilation.
2.4.1.2.2. Using RX in Adaptive Mode
Refer to the RX PMA sections of the Logical View of the L-Tile/H-Tile Transceiver Registers for more details on the register addresses, and the Intel® Stratix® 10 Dynamic Transceiver Reconfiguration chapter for details on the Avalon® memory-mapped interface and how to perform dynamic reads and writes to the analog PMA settings.
2.4.1.2.3. Setting RX PMA Adaptation Modes
There are a number of attributes that are configured differently across the RX adaptation modes. Refer to the Setting RX PMA Adaptation Modes resource for more details.
2.4.1.2.4. Register Sequences
When using the logical view register map to reconfigure the PMA, you must use the register addresses in the following sections:
- Pre-Emphasis: To change pre-emphasis manually
- VOD: to manually change VOD
- Manual CTLE: To change CTLE manually
- Manual VGA: To change VGA manually
- Adaptation Control - Start and Adaptation Control - Stop: To reset and start adaptation
- Adaptation Initial Values
- Adapted Value Readout: To read out the adapted CTLE, VGA, and DFE values
2.4.2. PCS Functions
2.4.2.1. Receiver Word Alignment
2.4.2.1.1. Word Alignment Using the Standard PCS
To achieve receiver word alignment, use the word aligner of the Standard PCS in one of the following modes:
- RX data bitslip
- Manual mode
- Synchronous State Machine
- Deterministic Latency Mode
- Word alignment in GbE Mode
RX Bitslip
To use the RX bitslip, select Enable rx_bitslip port and set the word aligner mode to bitslip. This adds rx_bitslip as an input control port. An active high edge on rx_bitslip slips one bit at a time. When rx_bitslip is toggled, the word aligner slips one bit at a time on every active high edge. Assert the rx_bitslip signal for at least 200 ns to ensure it passes through the slow shift register. You can verify this feature by monitoring rx_parallel_data.
The RX bitslip feature is optional and may or may not be enabled.
Refer to the Word Aligner bitslip Mode section for more information.
Word Aligner Manual Mode
Refer to the Intel® Stratix® 10 (L/H-Tile) Word Aligner Bitslip Calculator to calculate the number of slips you require to achieve alignment based on the word alignment pattern and length. To use this mode:
- Set the RX word aligner mode to Manual (FPGA Fabric controlled).
- Set the RX word aligner pattern length option according to the PCS-PMA interface width.
- Enter a hexadecimal value in the RX word aligner pattern (hex) field.
This mode adds rx_patterndetect and rx_syncstatus. You can select the Enable rx_std_wa_patternalign port option to enable rx_std_wa_patternalign.
- rx_patterndetect is asserted whenever there is a pattern match.
- rx_syncstatus is asserted after the word aligner achieves synchronization, 3 clkout cycles after rx_patterndetect goes high.
- rx_std_wa_patternalign is asserted to re-align and resynchronize.
- If there is more than one channel in the design, rx_patterndetect, rx_syncstatus and rx_std_wa_patternalign become buses in which each bit corresponds to one channel.
You can verify this feature by monitoring rx_parallel_data.
The following timing diagrams demonstrate how to use the ports and show the relationship between the various control and status signals. In the top waveform, rx_parallel_data is initially misaligned. After asserting the rx_std_wa_patternalign signal, it becomes aligned. The bottom waveform shows the behavior of the rx_syncstatus signal when rx_parallel_data is already aligned.
In manual alignment mode, the word alignment operation is manually controlled with the rx_std_wa_patternalign input signal or the rx_enapatternalign register. The word aligner operation is level-sensitive to rx_enapatternalign. The word aligner asserts the rx_syncstatus signal for one parallel clock cycle whenever it re-aligns to the new word boundary.
Refer to the Word Aligner Manual Mode section for more information.
Word Aligner Synchronous State Machine Mode
To use this mode:
- Select the Enable TX 8B/10B encoder option.
- Select the Enable RX 8B/10B decoder option.
The 8B/10B encoder and decoder add the following additional ports:
- tx_datak
- rx_datak
- rx_errdetect
- rx_disperr
- rx_runningdisp
- Set the RX word aligner mode to synchronous state machine.
- Set the RX word aligner pattern length option according to the PCS-PMA interface width.
- Enter a hexadecimal value in the RX word aligner pattern (hex) field.
The RX word aligner pattern is the 8B/10B encoded version of the data pattern. You can also specify the number of word alignment patterns (LSB first) to achieve synchronization, the number of invalid data words to lose synchronization, and the number of valid data words to decrement error count. This mode adds two additional ports: rx_patterndetect and rx_syncstatus.
- rx_patterndetect is asserted whenever there is a pattern match.
- rx_syncstatus is asserted after the word aligner achieves synchronization, 3 clkout cycles after rx_patterndetect goes high.
- If there is more than one channel in the design, tx_datak, rx_datak, rx_errdetect, rx_disperr, rx_runningdisp, rx_patterndetect, and rx_syncstatus become buses in which each bit corresponds to one channel.
You can verify this feature by monitoring rx_parallel_data.
Refer to the Word Aligner Synchronous State Machine Mode section for more information.
Word Aligner in Deterministic Latency Mode for CPRI
When using deterministic latency state machine mode, assert rx_std_wa_patternalign to initiate the pattern alignment after the reset sequence is complete. This is an edge-triggered signal in all cases except one: when the word aligner is in manual mode and the PMA width is 10 bits, in which case rx_std_wa_patternalign is level sensitive.
Calculating Latency through the Word Aligner
- Deterministic Latency State Machine (DLSM)
- Synchronous State Machine (SSM)
- Manual mode
- RX Bitslip mode
Word Alignment in GbE Mode
The Intel® Quartus® Prime Pro Edition software automatically configures the synchronization state machine to indicate synchronization when the receiver receives three consecutive synchronization ordered sets. A synchronization ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code groups. The fastest way for the receiver to achieve synchronization is to receive three continuous {/K28.5/, /Dx.y/} ordered sets.
The Native PHY IP core signals receiver synchronization status on the rx_syncstatus port of each channel. A high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out of synchronization. The receiver loses synchronization when it detects three invalid code groups separated by less than three valid code groups or when it is reset.
Synchronization State Machine Parameter | Setting |
---|---|
Number of word alignment patterns to achieve sync | 3 |
Number of invalid data words to lose sync | 3 |
Number of valid data words to decrement error count | 3 |
The following figure shows rx_syncstatus high when three consecutive ordered sets are sent through rx_parallel_data.
2.4.2.1.2. Word Alignment Using the Enhanced PCS
Refer to the Block Synchronizer section for more information.
Use the gearbox in the PCIe Gen3 PCS for 128B/130B as required by the PIPE Gen3 applications. Refer to the Gearbox section for more information.
2.4.2.2. Receiver Clock Compensation
2.4.2.2.1. Clock Compensation Using the Standard PCS
- Rate Match FIFO in Basic 10-bit PMA mode
- Rate Match FIFO in Basic 20-bit PMA mode
- Rate Match FIFO in GbE mode
- Rate Match FIFO in PIPE mode
- Rate Match FIFO in PIPE 0 ppm mode
Rate Match FIFO in Basic (Single Width) Mode
- Select basic (single width) in the RX rate match FIFO mode list.
-
Enter values for the following parameters.
Parameter Value Description RX rate match insert/delete +ve pattern (hex) 20 bits of data specified as a hexadecimal string The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity. RX rate match insert/delete –ve pattern (hex) 20 bits of data specified as a hexadecimal string The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity. ve (volt encodes) are NRZ_L conditions where +ve encodes 0 and –ve encodes 1. ve is a running disparity (+/–RD) specifically used with the rate matcher. Depending on the ppm difference (which is defined by protocol) between the recovered clock and the local clock, the rate matcher adds or deletes a maximum of four skip patterns (neutral disparity). The net neutrality is conserved even after the skip word insertion or deletion because the control words alternate between positive and negative disparity.
In the following figure, the first skip cluster has a /K28.5/ control pattern followed by two /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern followed by four /K28.0/ skip patterns. The rate match FIFO deletes only one /K28.0/ skip pattern from the first skip cluster to maintain at least one skip pattern in the cluster after deletion. Two /K28.0/ skip patterns are deleted from the second cluster for a total of three skip patterns deletion requirement.
The rate match FIFO can insert a maximum of four skip patterns in a cluster, if there are no more than five skip patterns in the cluster after insertion.
Figure 45. Rate Match FIFO Deletion with Three Skip Patterns Required for DeletionIn the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern followed by three /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern followed by two /K28.0/ skip patterns. The rate match FIFO inserts only two /K28.0/ skip patterns into the first skip cluster to maintain a maximum of five skip patterns in the cluster after insertion. One /K28.0/ skip pattern is inserted into the second cluster for a total of three skip patterns to meet the insertion requirement.
Figure 46. Rate Match FIFO Insertion with Three Skip Patterns Required for InsertionThe following figure shows the deletion of D5 when the upstream transmitter reference clock frequency is greater than the local receiver reference clock frequency. It asserts rx_std_rmfifo_full for one parallel clock cycle while the deletion takes place.
Figure 47. Rate Match FIFO Becoming Full After Receiving D5The following figure shows the insertion of skip symbols when the local receiver reference clock frequency is greater than the upstream transmitter reference clock frequency. It asserts rx_std_rmfifo_empty for one parallel clock cycle while the insertion takes place.
Figure 48. Rate Match FIFO Becoming Empty After Receiving D3
Rate Match FIFO Basic (Double Width) Mode
- Select basic (double width) in the RX rate match FIFO mode list.
-
Enter values for
the following parameters.
Parameter Value Description RX rate match insert/delete +ve pattern (hex) 20 bits of data specified as a hexadecimal string The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity. RX rate match insert/delete -ve pattern (hex) 20 bits of data specified as a hexadecimal string The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity. The rate match FIFO can delete as many pairs of skip patterns from a cluster as necessary to avoid the rate match FIFO from overflowing. The rate match FIFO can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip patterns appear straddled on the MSByte of a clock cycle and the LSByte of the next clock cycle, the rate match FIFO cannot delete the pair of skip patterns.
In the following figure, the first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle. The rate match FIFO cannot delete the two skip patterns in this skip cluster because they do not appear in the same clock cycle. The second skip cluster has a /K28.5/ control pattern in the MSByte of a clock cycle followed by two pairs of /K28.0/ skip patterns in the next two cycles. The rate match FIFO deletes both pairs of /K28.0/ skip patterns (for a total of four skip patterns deleted) from the second skip cluster to meet the three skip pattern deletion requirement.
The rate match FIFO can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match FIFO from under running. The 10-bit skip pattern can appear on the MSByte, the LSByte, or both, of the 20-bit word.
Figure 49. Rate Match FIFO Deletion with Four Skip Patterns Required for Deletion/K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle. The rate match FIFO inserts pairs of skip patterns in this skip cluster to meet the three skip pattern insertion requirement.
Figure 50. Rate Match FIFO Insertion with Four Skip Patterns Required for InsertionThe following figure shows the deletion of the 20-bit word D7D8.
Figure 51. Rate Match FIFO Becoming Full After Receiving the 20-Bit Word D5D6The following figure shows the insertion of two skip symbols.
Figure 52. Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6
Rate Match FIFO for GbE
The GbE protocol requires the transmitter to send Idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps (IPG) adhering to the rules listed in the IEEE 802.3-2008 specification.
The rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. The rate matcher deletes or inserts both symbols /K28.5/ and /D16.2/ of the /I2/ ordered sets as a pair in the operation to prevent the rate match FIFO from overflowing or underflowing. The rate match operation can insert or delete as many /I2/ ordered sets as necessary.
The following figure shows a rate match deletion operation example where three symbols must be deleted. Because the rate match FIFO can only delete /I2/ ordered sets, it deletes two /I2/ ordered sets (four symbols deleted).
The following figure shows an example of rate match FIFO insertion in the case where one symbol must be inserted. Because the rate match FIFO can only insert /I2/ ordered sets, it inserts one /I2/ ordered set (two symbols inserted).
rx_std_rmfifo_full and rx_std_rmfifo_empty are forwarded to the FPGA fabric to indicate rate match FIFO full and empty conditions.
The rate match FIFO does not delete code groups to overcome a FIFO full condition. It asserts the rx_std_rmfifo_full flag for at least two recovered clock cycles to indicate rate match FIFO full. The following figure shows the rate match FIFO full condition when the write pointer is faster than the read pointer.
The rate match FIFO does not insert code groups to overcome the FIFO empty condition. It asserts the rx_std_rmfifo_empty flag for at least two recovered clock cycles to indicate that the rate match FIFO is empty. The following figure shows the rate match FIFO empty condition when the read pointer is faster than the write pointer.
In the case of rate match FIFO full and empty conditions, you must assert the rx_digitalreset signal to reset the receiver PCS blocks.
Clock Compensation for PIPE
Refer to the Gen1 and Gen2 Clock Compensation and Gen3 Clock Compensation sections for more information.