Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

6.5. The HyperRAM Tab

The HyperRAM tab allows you to test the HyperRAM by reading and writing to a selected number of addresses with selectable burst length. The supported burst lengths are 2, 4, 8, 16, 32, 64, and 128.
Figure 21. The HyperRAM Tab
Table 30.  The HyperRAM Tab Controls
Control Description
Speed (MByte/s)
  • Write, Read, and Total—Show the number of bytes of data analyzed per second.

    The data bus is 8 bits wide and the frequency is 150 MHz double data rate. With 300 megabits per second (Mbps) per pin, the theoretical maximum bandwidth is 2400 Mbps or 300 MByte/s.

Errors These controls display data errors detected during analysis and allow you to insert errors.
  • Detected—Displays the number of data errors detected in the hardware.
  • Inserted—Displays the number of errors inserted into the transaction stream.
  • Insert—Inserts a one-word error into the transaction stream each time you click the button. Insert is only enabled during transaction performance analysis.
    Note: For Address Range of 16 MB, ensure the interval between two clicks on Insert button is larger than the one during testing.
  • Clear—Resets the Detected errors and Inserted errors counters to zeroes.
Address Range (Bytes) Determines the number of addresses to use in each iteration of reads and writes.
Test Times This item displays test times since you last clicked Start.
Control
  • Burst Length—Allows you to change the burst length of the design. Supported burst lengths are 2, 4, 8, 16, 32, 64, and 128.
  • Start—Start HyperRAM testing
  • Stop—Stop HyperRAM testing
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