Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

ID 683580
Date 12/19/2019
Document Table of Contents

6.5. The HyperRAM Tab

The HyperRAM tab allows you to test the HyperRAM by reading and writing to a selected number of addresses with selectable burst length. The supported burst lengths are 2, 4, 8, 16, 32, 64, and 128.
Figure 21. The HyperRAM Tab
Table 30.  The HyperRAM Tab Controls
Control Description
Speed (MByte/s)
  • Write, Read, and Total—Show the number of bytes of data analyzed per second.

    The data bus is 8 bits wide and the frequency is 150 MHz double data rate. With 300 megabits per second (Mbps) per pin, the theoretical maximum bandwidth is 2400 Mbps or 300 MByte/s.

Errors These controls display data errors detected during analysis and allow you to insert errors.
  • Detected—Displays the number of data errors detected in the hardware.
  • Inserted—Displays the number of errors inserted into the transaction stream.
  • Insert—Inserts a one-word error into the transaction stream each time you click the button. Insert is only enabled during transaction performance analysis.
    Note: For Address Range of 16 MB, ensure the interval between two clicks on Insert button is larger than the one during testing.
  • Clear—Resets the Detected errors and Inserted errors counters to zeroes.
Address Range (Bytes) Determines the number of addresses to use in each iteration of reads and writes.
Test Times This item displays test times since you last clicked Start.
  • Burst Length—Allows you to change the burst length of the design. Supported burst lengths are 2, 4, 8, 16, 32, 64, and 128.
  • Start—Start HyperRAM testing
  • Stop—Stop HyperRAM testing