Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 11/18/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System 7. Document Revision History for the Cyclone® 10 LP FPGA Evaluation Kit User Guide A. Safety and Regulatory Compliance Information
1. Overview x
1.1. Feature Summary 1.2. Box Contents 1.3. Evaluation Board Revisions 1.4. Recommended Operating Conditions
1.2. Box Contents x
1.2.1. Power Supply Description
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Evaluation Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Cyclone® 10 LP FPGA Overview 4.3. MAX® 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus® Prime Programmer 4.4.2. Program Onboard EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital I/Os 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The Sys Info Tab 6.3. The GPIO Tab 6.4. The FLASH Tab 6.5. The HRAM Tab 6.6. The Power Monitor 6.7. The Clock Controller
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
7. Document Revision History for the Cyclone® 10 LP FPGA Evaluation Kit User Guide
A. Safety and Regulatory Compliance Information

4.4. FPGA Configuration

The Cyclone® 10 LP FPGA Evaluation Board supports two configuration methods:
  • Configuration by downloading a .sof file to the FPGA. Any power cycling of the FPGA or reconfiguration can power up the FPGA to a blank state.
  • Programming of the board EPCQ or EPCQ-A flash with a .jic file. Any power cycling of the FPGA or reconfiguration can lead to reconfigure from flash with AS mode.
You can use two different Intel® FPGA Download Cable hardware components to program the .sof or .jic files:
  • Embedded Intel® FPGA Download Cable II type-B mini-USB connector (J17)
  • JTAG header (J2). Use an external Intel® FPGA Download Cable, Intel® FPGA Download Cable II or Ethernet Blaster download cable. The external download cable connects to the board through the JTAG header (J2).

Section Content
Using the Quartus Prime Programmer
Program Onboard EPCQ or EPCQ-A Flash Memory
Active Serial Configuration

Level Two Title