Cyclone® 10 LP FPGA Evaluation Kit User Guide

Download PDF
ID 683580
Date 11/18/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System 7. Document Revision History for the Cyclone® 10 LP FPGA Evaluation Kit User Guide A. Safety and Regulatory Compliance Information
1. Overview x
1.1. Feature Summary 1.2. Box Contents 1.3. Evaluation Board Revisions 1.4. Recommended Operating Conditions
1.2. Box Contents x
1.2.1. Power Supply Description
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Evaluation Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Cyclone® 10 LP FPGA Overview 4.3. MAX® 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus® Prime Programmer 4.4.2. Program Onboard EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital I/Os 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The Sys Info Tab 6.3. The GPIO Tab 6.4. The FLASH Tab 6.5. The HRAM Tab 6.6. The Power Monitor 6.7. The Clock Controller
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
7. Document Revision History for the Cyclone® 10 LP FPGA Evaluation Kit User Guide
A. Safety and Regulatory Compliance Information

7. Document Revision History for the Cyclone® 10 LP FPGA Evaluation Kit User Guide

Version Description
2025.11.18
  • Updated the Overview chapter:
    • Updated and retitled topic Evaluation Board Description to Feature Summary.
    • Updated and retitled topic Evaluation Kit Description to Box Contents.
    • Moved the topic Handling the Board to the Getting Started chapter.
    • Removed topic Evaluation Kit Collateral.
  • Updated the Getting Started chapter:
    • Added new topics:
      • Before You Begin
      • Handling the DIP Switch
    • Updated and retitled topic Installing Quartus Prime Software to Installing the Quartus® Prime Standard Edition Software.
    • Updated and retitled topic Installing the Evaluation Kit Collateral to Installing the Evaluation Kit.
  • Updated the Updated the Board Test System chapter:
    • Retitled topic The System Info Tab to The Sys Info Tab.
    • Retitled topic The HyperRAM Tab to The HRAM Tab.
    • Retitled topic The Clock Control to The Clock Controller.
  • Combined the safety and regulatory and compliance topics under one appendix chapter—Safety and Regulatory Compliance Information.
  • Updated document for the latest branding standards.
  • Made editorial edits throughout the document.
2019.12.19

Note added to inform users to contact Synaptic Labs to download HBMC license and latest version of HMBC IP. Updated HyperRAM.
2018.02.05
  • This user guide supports Rev A1 and Rev A2 evaluation boards:
    • Rev A1: 64 Mb EPCQ flash, ISSI IS66WVH16M8ALL-166B1LI HyperRAM
    • Rev A2: 128 Mb EPCQ-A flash, Cypress S70KS1281DPBHI020 HyperRAM
  • Correction to Quartus® Prime support: the Cyclone® 10 LP device is supported only by Quartus® Prime Standard Edition software
  • New chapter: "Simple Socket Server"
  • New section in "Evaluation Board Setup" chapter: "Factory Reset"
  • Changes and additions to BTS GUI
  • Added the following illustrations:
    • " Cyclone® 10 LP Evaluation Board Part Number Label"
    • "Board Test System GUI with Restore Menu"
    • "Restoring Factory Defaults on the Cyclone® 10 LP LP FPGA Evaluation Board"
  • Updated the following illustrations:
    • " Cyclone® 10 LP FPGA Evaluation Board Block Diagram"
    • "Arduino Connector"
    • "Accessing telnet from the Nios II Command Shell"
    • "Board Test System (BTS) Graphical User Interface (GUI)"
    • "The Configure Menu"
    • "The System Info Tab"
    • "The GPIO Tab"
    • "The Flash Tab"
    • "The HyperRAM Tab"
    • "The Power Monitor"
    • "The Si5351 Tab"
2017.08.23 Preliminary Release
Level Two Title