Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

ID 683580
Date 12/19/2019
Document Table of Contents

4.10.2. EPCQ or EPCQ-A Flash Memory

The Intel® Cyclone® 10 LP FPGA Evaluation board has an Intel® 64 Mb EPCQ64 or 128 Mb EPCQ128A in-system programmable NOR flash for non-volatile storage of the FPGA configuration data, board information, test application data and user code space.

Depending on its revision, your board has one of two flash memory devices: EPCQ64 or EPCQ128A. To determine which device you have, refer to "Evaluation Board Revisions".

Although the quad-serial flash provided has a ×4 data width, the evaluation board has a ×1 data width because the Intel® Cyclone® 10 LP FPGA only supports an AS ×1 configuration scheme. Other data signals are tied to 3.3 V power required by the device datasheet.

The table below shows the memory map for this flash memory. This memory provides non-volatile storage for FPGA bit stream, Nios® II factory software and other information.

Table 25.  Flash Memory Map
Block Description Size (KB) Address Comments
Board Test System Scratch 512 0x0073.0000 - 0x007A.FFFF BTS System Testing
Board Information 64 0x0072.0000 - 0x0072.FFFF Board Information
Ethernet Option Bits 64 0x0071.0000 - 0x0071.FFFF MAC Address Information
User Design Reset Vector 64 0x0070.0000 - 0x0070.FFFF Nios II Reset Vector Information
Factory Software (ELF) 4096 0x0030.0000 - 0x006F.FFFF Software File
Factory Hardware (sof) 3072 0x0000.0000 - 0x002F.FFFF SOF File
Total 7872    

The signal connections between the Intel® Cyclone® 10 LP FPGA and flash comply with the AS ×1 configuration requirements.

Table 26.  Signal Connections
Flash Pin Number Schematic Signal Name FPGA Pin Number I/O Standard Description
U2.16 C10_AS_DCLK U1.H1 3.3 V FPGA Clock Output
U2.7 C10_AS_CSn U1.D2 3.3 V FPGA Chip Select Output
U2.8 C10_AS_DATA0 U1.H2 3.3 V FPGA Data Input
U2.15 C10_AS_ASDO U1.C1 3.3 V FPGA Data and Control Signals Output
Note: When using a serial flash loader (SFL) core and the Intel® Quartus® Prime Programmer to erase and program the flash, virtual JTAG must be bypassed by setting the SW1.4 switch to ON. Signal Net VTAP_BYPASSn is logic 0.