Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

Download PDF
ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

4.2. Intel® Cyclone® 10 LP FPGA Overview

The Intel® Cyclone® 10 LP FPGA Evaluation Board features the Intel® Cyclone® 10 LP 10CL025YU256I7G FPGA device in a 256 pin Ultra FineLine BGA package.

The Intel® Cyclone® 10 LP FPGAs are optimized for low cost and low static power, making them ideal for high-volume and cost-sensitive applications.

Table 5.   Intel® Cyclone® 10 LP FPGA
Equivalent LEs M9K Memory Blocks M9K Memory Size (Kb) 18-bit x 18-bit multipliers PLLs Transceivers Package Type
25K 66 594 66 4 --- 256-pin UBGA (14 mm x 14 mm, 0.8 mm pitch)

Intel® Cyclone® 10 LP FPGA Feature Summary

Intel® Cyclone® 10 LP FPGA devices provide a high-density sea of programmable gates, on-board resources, and general purpose I/Os. These resources satisfy the requirements of I/O expansion and chip-to-chip interfacing. The Intel® Cyclone® 10 LP FPGA architecture suits smart and connected end applications across many market segments:
  • Industrial and automotive
  • Broadcast, wireline, and wireless
  • Compute and storage
  • Government, military, and aerospace
  • Medical, consumer, and smart energy
Table 6.  Summary of Features for Intel® Cyclone® 10 LP FPGA Devices
Feature Description

Technology

  • Low-cost, low-power FPGA fabric
  • 1.0 V and 1.2 V core voltage options
  • Available in commercial, industrial, and automotive temperature grades

Packaging

  • Several package types and footprints:
    • FineLine BGA (FBGA)
    • Enhanced Thin Quad Flat Pack (EQFP)
    • Ultra FineLine BGA (UBGA)
    • Micro FineLine BGA (MBGA)
  • Multiple device densities with pin migration capability
  • RoHS6 compliance

Core architecture
  • Logic elements (LEs)—four-input look-up table (LUT) and register
  • Abundant routing/metal interconnect between all LEs

Internal memory blocks

  • M9K—9-kilobits (Kb) of embedded SRAM memory blocks, cascadable
  • Configurable as RAM (single-port, simple dual port, or true dual port), FIFO buffers, or ROM
Embedded multiplier blocks
  • One 18 × 18 or two 9 × 9 multiplier modes, cascadable
  • Complete suite of DSP IPs for algorithmic acceleration

Clock networks

  • Global clocks that drive throughout entire device, feeding all device quadrants
  • Up to 15 dedicated clock pins that can drive up to 20 global clocks

Phase-locked loops (PLLs)

  • Up to four general purpose PLLs
  • Provides robust clock management and synthesis

General-purpose I/Os (GPIOs)

  • Multiple I/O standards support
  • Programmable I/O features
  • True LVDS and emulated LVDS transmitters and receivers
  • On-chip termination (OCT)
SEU mitigation SEU detection during configuration and operation

Configuration

  • Active serial (AS), passive serial (PS), fast passive parallel (FPP)
  • JTAG configuration scheme
  • Configuration data decompression
  • Remote system upgrade
Related Information
Level Two Title