Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

ID 683580
Date 12/19/2019
Document Table of Contents

4.3. MAX 10 System Controller Overview

The highlights of the Intel® MAX® 10 devices include:
  • Internally stored dual configuration flash
  • User flash memory
  • Instant on support
  • Integrated analog-to-digital converter (ADC)
  • Single-chip Nios II soft core processor support

Intel® MAX® 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Table 7.   Summary of Features for Intel® MAX® 10 Devices
Feature Description
Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process technology
  • Low cost, small form factor packages—support multiple packaging technologies and pin pitches
  • Multiple device densities with compatible package footprints for seamless migration between different device densities
  • RoHS6-compliant
Core architecture
  • 4-input look-up table (LUT) and single register logic element (LE)
  • LEs arranged in logic array block (LAB)
  • Embedded RAM and user flash memory
  • Clocks and PLLs
  • Embedded multiplier blocks
  • General purpose I/Os
Internal memory blocks
  • M9K—9 kilobits (Kb) memory blocks
  • Cascadable blocks to create RAM, dual port, and FIFO functions
User flash memory (UFM)
  • User accessible non-volatile storage
  • High speed operating frequency
  • Large memory size
  • High data retention
  • Multiple interface option
Embedded multiplier blocks
  • One 18 × 18 or two 9 × 9 multiplier modes
  • Cascadable blocks enabling creation of filters, arithmetic functions, and image processing pipelines
  • 12-bit successive approximation register (SAR) type
  • Up to 16 analog inputs
  • Cumulative speed up to 1 million samples per second (MSPS)
  • Integrated temperature sensing capability
Clock networks
  • Global clocks support
  • High speed frequency in clock network
Internal oscillator Built-in internal ring oscillator
  • Analog-based
  • Low jitter
  • High precision clock synthesis
  • Clock delay compensation
  • Zero delay buffering
  • Multiple output taps
General-purpose I/Os (GPIOs)
  • Multiple I/O standards support
  • On-chip termination (OCT)
  • Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitter
External memory interface (EMIF) Supports up to 600 Mbps external memory interfaces:
  • SRAM (Hardware support only)
Note: For 600 Mbps performance, –6 device speed grade is required. Performance varies according to device grade (commercial, industrial, or automotive) and device speed grade (–6 or –7). Refer to the MAX 10 Device Data Sheet or External Memory Interface Spec Estimator for more details.
  • Internal configuration
  • JTAG
  • Advanced Encryption Standard (AES) 128-bit encryption and compression options
  • Flash memory data retention of 20 years at 85 °C
Flexible power supply schemes
  • Single- and dual-supply device options
  • Dynamically controlled input buffer power down
  • Sleep mode for dynamic power reduction