Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 12/01/2021
Public

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2.7. Traffic Generator and Checker

Figure 34. Traffic Generator and Checker

This design example instantiates the Traffic Generator and Checker for MCDMA module (BAS_TGC) that creates read and write transactions to exercise the Bursting Avalon-MM Slave module of the Multi Channel DMA for PCI Express* IP configured in BAM+BAS mode. You can program the BAS_TGC by writing to its control registers through its Control and Status Avalon-MM slave interface. The traffic that it generates, and the traffic that checker expects is in a sequence of incrementing dwords.

For traffic generation, the host software allocates a block of memory in the PCIe* space and then programs one of the windows in the Address Mapper to point to the allocated memory block. It also needs to set the start address which is the base address of the selected space for write transactions, set the write count to the size of the block of the allocated memory block, and set the transfer size before kick start to the traffic generation. The number of completed transfers can be checked by reading the write count register.

For traffic checking, the host software sets the read address to point to the start address of the write transactions, set the read count to the size of the block of the allocated memory block, and set the transfer size before kick start to the traffic checker. The number of completed data check and the number of errors occurred can be checked by reading the read count and read error count registers, respectively.

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