Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 12/01/2021

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Document Table of Contents BAM Test

If the BAM support is enabled on hardware, enable the following flag in common/mk/

__cflags += -DIFC_PIO_256 → 256b read/write operations on PIO BAR

__cflags += -DIFC_PIO_128 → 128b read/write operations on PIO BAR

To enable 256b read/write operations, this is the difference in
Command: ./cli/perfq_app/perfq_app -b 0000:86:00.0 -o
To enable 128b read/write operations:

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